SNOSDE3C July   2023  – April 2024 TPS7H6003-SP , TPS7H6013-SP , TPS7H6023-SP

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Device Comparison Table
  6. Device Options Table
  7. Pin Configuration and Functions
  8. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Quality Conformance Inspection
    8. 7.8 Typical Characteristics
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Input Voltage
      2. 8.3.2  Linear Regulator Operation
      3. 8.3.3  Bootstrap Operation
        1. 8.3.3.1 Bootstrap Charging
        2. 8.3.3.2 Bootstrap Capacitor
        3. 8.3.3.3 Bootstrap Diode
        4. 8.3.3.4 Bootstrap Resistor
      4. 8.3.4  High-Side Driver Startup
      5. 8.3.5  Inputs and Outputs
      6. 8.3.6  Dead Time
      7. 8.3.7  Input Interlock Protection
      8. 8.3.8  Undervoltage Lockout and Power Good (PGOOD)
      9. 8.3.9  Negative SW Voltage Transients
      10. 8.3.10 Level Shifter
    4. 8.4 Device Functional Modes
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Bootstrap and Bypass Capacitors
        2. 9.2.2.2 Bootstrap Diode
        3. 9.2.2.3 BP5x Overshoot and Undershoot
        4. 9.2.2.4 Gate Resistor
        5. 9.2.2.5 Dead Time Resistor
        6. 9.2.2.6 Gate Driver Losses
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Examples
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • HBX|48
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Device Functional Modes

The mode of operation for the TPS7H60x3-SP is determined by the state of the DHL and DLH pins. The configuration of these pins should not be changed during device operation. There are two different operational modes: PWM and independent input mode. In PWM mode, the EN_HI pin is used to enable the device and a single PWM input signal is required on PWM_LI and the TPS7H60x3-SP generates the complementary output signals on LO and HO. Since the primary application of this mode is a synchronous buck converter, HO will generate the main output and LO will generate the synchronous rectification output. Resistors are connected from DHL to AGND and DLH to AGND in order to program the dead time between the high-side and low-side outputs. For acceptable resistor values (TBD) to use in PWM mode, refer to Dead Time section.

In independent input mode (IIM), separate PWM input signals are required on PWM_LI and EN_HI. The corresponding outputs of the TPS7H60x3-SP are driven directly from these inputs. In IIM with interlock disabled, DLH is tied to BP5L and DHL has a resistor connected to AGND. For operation in IIM with interlock enabled, connect a resistor between DLH and AGND while connecting DHL to BP5L. For both operating mode options in IIM, resistors used must be valued between 100 kΩ and 220 kΩ.

Table 8-1 shows the configuration for each operating mode. Note that these are the only valid operating modes for the driver, and the connections for DLH and DHL must adhere to one of these configurations for proper operation.

Table 8-1 TPS7H60x3-SP Operating Mode Selection
Operating Mode DLH DHL
PWM Resistor to AGND Resistor to AGND
Independent input mode - input interlock disabled BP5L Resistor to AGND (100 kΩ to 220 kΩ)
Independent input mode - input interlock enabled Resistor to AGND (100 kΩ to 220 kΩ) BP5L

Table 8-2 shows the truth table for each functional mode of the TPS7H60x3-SP.

Table 8-2 TPS7H60x3-SP Truth Table
Inputs PWM Mode IIM - Interlock Disabled IIM - Interlock Enabled
EN_HI PWM_LI HO LO HO LO HO LO
0 0 0 0 0 0 0 0
0 1 0 0 0 1 0 1
1 0 0 1 1 0 1 0
1 1 1 0 1 1 0 0