SNOSDE3C July   2023  – April 2024 TPS7H6003-SP , TPS7H6013-SP , TPS7H6023-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Device Options Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Quality Conformance Inspection
    8. 7.8 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Input Voltage
      2. 8.3.2  Linear Regulator Operation
      3. 8.3.3  Bootstrap Operation
        1. 8.3.3.1 Bootstrap Charging
        2. 8.3.3.2 Bootstrap Capacitor
        3. 8.3.3.3 Bootstrap Diode
        4. 8.3.3.4 Bootstrap Resistor
      4. 8.3.4  High-Side Driver Startup
      5. 8.3.5  Inputs and Outputs
      6. 8.3.6  Dead Time
      7. 8.3.7  Input Interlock Protection
      8. 8.3.8  Undervoltage Lockout and Power Good (PGOOD)
      9. 8.3.9  Negative SW Voltage Transients
      10. 8.3.10 Level Shifter
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Bootstrap and Bypass Capacitors
        2. 9.2.2.2 Bootstrap Diode
        3. 9.2.2.3 BP5x Overshoot and Undershoot
        4. 9.2.2.4 Gate Resistor
        5. 9.2.2.5 Dead Time Resistor
        6. 9.2.2.6 Gate Driver Losses
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Examples
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • HBX|48
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.3.2 Bootstrap Capacitor

The external bootstrap capacitor that is required for the driver is connected between BOOT and ASW. The bootstrap capacitor voltage serves as the input to the high-side linear regulator BP5H that provides the gate drive voltage for the high-side GaN FET. A general guideline for bootstrap capacitor selection is that its value should be at least 10× greater than the gate capacitance of the high-side GaN FET that is being driven:

Equation 1. C B O O T ≥ 10   × C g

where:

  • Cg is the gate capacitance for the high-side GaN FET

A more detailed calculation of the minimum bootstrap capacitance needed can be found using Equation 2:

Equation 2. C B O O T ≥ Q t o t a l ∆ V B O O T
Equation 3. Q t o t a l = Q g + I Q B G × D M A X f S W + I Q H S f S W

where:

  • Qg is the total gate charge for the high-side GaN FET
  • IQBG is the BOOT to AGND quiescent current
  • DMAX is the maximum duty cycle
  • IQHS is the high-side quiescent current
  • fSW is the switching frequency

and ∆VBOOT is the maximum allowable drop on BOOT for proper operation:

Equation 4. ∆ V B O O T = V I N - n × V F - V B O O T _ U V L O

where:

  • VIN is the gate driver input voltage
  • n is the number of external bootstrap diodes placed in series
  • VF is the forward voltage drop of the bootstrap diode
  • VBOOT_UVLO is the falling undervoltage lockout threshold of BOOT (6.65 V typical)

Selection of a bootstrap capacitor with low ESR and ESL is recommended. The voltage rating of the bootstrap capacitor should have sufficient margin above the maximum expected bootstrap voltage.