SNOSDE3C July   2023  – April 2024 TPS7H6003-SP , TPS7H6013-SP , TPS7H6023-SP

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Device Comparison Table
  6. Device Options Table
  7. Pin Configuration and Functions
  8. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Quality Conformance Inspection
    8. 7.8 Typical Characteristics
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Input Voltage
      2. 8.3.2  Linear Regulator Operation
      3. 8.3.3  Bootstrap Operation
        1. 8.3.3.1 Bootstrap Charging
        2. 8.3.3.2 Bootstrap Capacitor
        3. 8.3.3.3 Bootstrap Diode
        4. 8.3.3.4 Bootstrap Resistor
      4. 8.3.4  High-Side Driver Startup
      5. 8.3.5  Inputs and Outputs
      6. 8.3.6  Dead Time
      7. 8.3.7  Input Interlock Protection
      8. 8.3.8  Undervoltage Lockout and Power Good (PGOOD)
      9. 8.3.9  Negative SW Voltage Transients
      10. 8.3.10 Level Shifter
    4. 8.4 Device Functional Modes
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Bootstrap and Bypass Capacitors
        2. 9.2.2.2 Bootstrap Diode
        3. 9.2.2.3 BP5x Overshoot and Undershoot
        4. 9.2.2.4 Gate Resistor
        5. 9.2.2.5 Dead Time Resistor
        6. 9.2.2.6 Gate Driver Losses
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Examples
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • HBX|48
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Gate Driver Losses

Gate drive devices such as the TPS7H6003-SP have several different components that comprise the power losses. The quiescent power losses PQCcan be determined using Equation 21 :

Equation 21. PQC=VIN×IQLS+VBOOT×IQHS=12 V×5 mA+10 V ×4 mA=100 mW

where:

  • IQLS is the low-side quiescent current (selected for PWM mode in this design)
  • IQHS is the high-side quiescent current (selected for PWM mode in this design)
  • VBOOT is the voltage at BOOT with respect to ASW

Leakage current power losses PBG can be calculated using Equation 22 :

Equation 22. PBG=VBG×IQBG×DMAX=110 V ×50 μA×0.35=0.77 mW

where:

  • VBG is the voltage between BOOT and AGND
  • IQBG is the BOOT to AGND leakage current

There are losses that occur within the driver due to the charging and discharging of the GaN FET gate charge. To determine these, first calculate PGATE as:

Equation 23. PGATE=VBP5x×QG×fSW=5 V ×10.6 nC×500 kHz=26.5 mW

This loss is actually distributed amongst the resistances in the gate driver loop, which includes the driver, the gate resistances and the GaN FET. The power dissipated within the TPS7H6003-SP for both turn-on and turn-off can be calculated:

Equation 24. PDRV_ON_HS=12×RHOH×PGATERHOH+RGATE+RGFET(int)
Equation 25. PDRV_OFF_HS=12×RHOL×PGATERHOL+RGATE+RGFET(int)
Equation 26. PDRV_ON_LS=12×RLOH×PGATERLOH+RGATE+RGFET(int)
Equation 27. PDRV_OFF_LS=12×RLOL×PGATERLOL+RGATE+RGFET(int)

In this instance, the high-side and low-side losses are the same:

Equation 28. PDRV_ON_HS=PDRV_ON_LS=12×RxOH×PGATERxOH+RGATE+RGFET(int)=12×1.3 Ω×26.5 mW1.3 Ω+2 Ω+0.4 Ω=4.7 mW
Equation 29. PDRV_OFF_HS=PDRV_OFF_LS=12×RxOL×PGATERxOL+RGATE+RGFET(int)=12×0.07 Ω×26.5 mW0.07 Ω+2 Ω+0.4 Ω=0.8 mW

Finally, the PGATE losses within the driver can be found:

Equation 30. PDRV_HS=PDRV_ON_HS+PDRV_OFF_HS=4.7 mW+0.8 mW=5.5 mW
Equation 31. PDRV_LS=PDRV_ON_LS+PDRV_OFF_LS=4.7 mW+0.8 mW=5.5 mW
Equation 32. PDRV=PDRV_HS+PDRV_LS=5.5 mW+5.5 mW=11 mW

There is also a component power consumption associated with the operating current of the driver itself, which is specified at no-load and frequency dependent. These can be approximated using the operating current parameters in the Specifications section:

Equation 33. POP_PWM=VIN×IOP_PWM_LS+VBOOT×IOP_PWM_HS=12 V×6 mA+10 V×5 mA=122 mW

where:

  • IOP_PWM_LS is the low-side operating current (selected for PWM mode at 500 kHz)
  • IOP_PWM_HS is the high-side operating current (selected for PWM mode at 500 kHz)