SNOSDH4A June 2024 – December 2024 TPS7H6005-SEP , TPS7H6015-SEP , TPS7H6025-SEP
PRODMIX
Refer to the PDF data sheet for device specific package drawings
The mode of operation for the TPS7H60x5 is determined by the state of the DHL and DLH pins. The configuration of these pins should not be changed during device operation. There are two different operational modes: PWM and independent input mode. In PWM mode, the EN_HI pin is used to enable the device and a single PWM input signal is required on PWM_LI and the TPS7H6005 generates the complementary output signals on LO and HO. Since the primary application of this mode is a synchronous buck converter, HO will generate the main output and LO will generate the synchronous rectification output. Resistors are connected from DHL to AGND and DLH to AGND in order to program the dead time between the high-side and low-side outputs. For acceptable resistor values (TBD) to use in PWM mode, refer to Dead Time section.
In independent input mode (IIM), separate PWM input signals are required on PWM_LI and EN_HI. The corresponding outputs of the TPS7H60x5 are driven directly from these inputs. In IIM with interlock disabled, DLH is tied to BP5L and DHL has a resistor connected to AGND. For operation in IIM with interlock enabled, connect a resistor between DLH and AGND while connecting DHL to BP5L. For both operating mode options in IIM, resistors used must be valued between 100kΩ and 220kΩ.
Table 8-1 shows the configuration for each operating mode. Note that these are the only valid operating modes for the driver, and the connections for DLH and DHL must adhere to one of these configurations for proper operation.
Operating Mode | DLH | DHL |
---|---|---|
PWM | Resistor to AGND | Resistor to AGND |
Independent input mode - input interlock disabled | BP5L | Resistor to AGND (100kΩ to 220kΩ) |
Independent input mode - input interlock enabled | Resistor to AGND (100kΩ to 220kΩ) | BP5L |
Table 8-2 shows the truth table for each functional mode of the TPS7H60x5.
Inputs | PWM Mode | IIM - Interlock Disabled | IIM - Interlock Enabled | ||||
---|---|---|---|---|---|---|---|
EN_HI | PWM_LI | HO | LO | HO | LO | HO | LO |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 |
1 | 0 | 0 | 1 | 1 | 0 | 1 | 0 |
1 | 1 | 1 | 0 | 1 | 1 | 0 | 0 |