SNOSDH4 Data sheet

SNOSDH4A June 2024 – December 2024 TPS7H6005-SEP , TPS7H6015-SEP , TPS7H6025-SEP

PRODMIX

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)

DCA|56

Thermal pad, mechanical data (Package|Pins)

Orderable Information

snosdh4a_oa

9.2.2.4 Gate Resistor

The TPS7H6005 has split outputs, allowing for resistors to be placed in series with the gate of the GaN FET in both the turn-on and turn-off paths. These gate resistors serve to dampen ringing at the gate of the device that is caused by parasitic capacitances and inductances. Ringing and noise can also be presented due to the high voltage and current switching in the gate drive power loop. This is particularly important for GaN devices which have low values for the absolute maximum gate voltages. Furthermore, the gate resistors can also be used to tune the drive strength of the drive. This is done by limiting the peak current capability of the driver. For this design, 2Ω resistors are used for both the turn-on and turn-off gate paths. From these values, the high-side peak pull-up current can be calculated as shown in :

Equation 13.

I_{O H H} = M I N (1.3 A, \frac{V_{B P 5 H}}{R_{H O H} + R_{G A T E_O N} + R_{G F E T (i n t)}})

where:

V_BP5H is the output voltage of the high side linear regulator
R_HOH is the internal high-side pull-up resistance (1.3Ω calculated from the high-level output voltage specification)
R_{GATE_ON} is the gate resistor value used in the turn-on path
R_GFET(int) is the internal gate resistance of the GaN FET being driven (typically available from the GaN FET manufacturer)

Note that as indicated in the Specifications section, the peak source current the driver is capable of providing is approximately 1.3A (typical), so I_OHH is limited by this value. In this instance:

Equation 14.

I_{O H H} = \frac{V_{B P 5 H}}{R_{H O H} + R_{G A T E_O N} + R_{G F E T (i n t)}} = \frac{5 V}{1.3 Ω + 2 Ω + 0.4 Ω} \approx 1.3 A

Likewise, for the peak high-side sink current:

Equation 15.

I_{O L H} = M I N (2.5 A, \frac{V_{B P 5 H}}{R_{H O L} + R_{G A T E_O F F} + R_{G F E T (i n t)}})

where:

R_HOL is the internal high-side pull-down resistance (0.7Ω calculated from the low-level output voltage specification)
R_{GATE_OFF} is the gate resistor value used in the turn-off path

As such, the peak sink current can be calculated as:

Equation 16.

I_{O L H} = \frac{V_{B P 5 H}}{R_{H O L} + R_{G A T E_O F F} + R_{G F E T (i n t)}} = \frac{5 V}{0.7 Ω + 2 Ω + 0.4 Ω} = 1.6 A

The equations for the low-side peak source and sink current are provided, but note that in this instance these are identical to the high-side values calculated.

Equation 17.

I_{O H L} = M I N (1.3 A, \frac{V_{B P 5 L}}{R_{L O H} + R_{G A T E_O N} + R_{G F E T (i n t)}}) = \frac{5 V}{1.3 Ω + 2 Ω + 0.4 Ω} \approx 1.3 A

Equation 18.

I_{O L L} = M I N (2.5 A, \frac{V_{B P 5 L}}{R_{L O L} + R_{G A T E_O F F} + R_{G F E T (i n t)}}) = \frac{5 V}{0.7 Ω + 2 Ω + 0.4 Ω} = 1.6 A

The selection of the external gate resistor typically requires tuning and is an iterative process. The best practice is to evaluate the value of the gate resistors on the specific PCB design to verify the intended impact and adjust as needed.