SNOSDE3C July   2023  – April 2024 TPS7H6003-SP , TPS7H6013-SP , TPS7H6023-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Device Options Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Quality Conformance Inspection
    8. 7.8 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Input Voltage
      2. 8.3.2  Linear Regulator Operation
      3. 8.3.3  Bootstrap Operation
        1. 8.3.3.1 Bootstrap Charging
        2. 8.3.3.2 Bootstrap Capacitor
        3. 8.3.3.3 Bootstrap Diode
        4. 8.3.3.4 Bootstrap Resistor
      4. 8.3.4  High-Side Driver Startup
      5. 8.3.5  Inputs and Outputs
      6. 8.3.6  Dead Time
      7. 8.3.7  Input Interlock Protection
      8. 8.3.8  Undervoltage Lockout and Power Good (PGOOD)
      9. 8.3.9  Negative SW Voltage Transients
      10. 8.3.10 Level Shifter
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Bootstrap and Bypass Capacitors
        2. 9.2.2.2 Bootstrap Diode
        3. 9.2.2.3 BP5x Overshoot and Undershoot
        4. 9.2.2.4 Gate Resistor
        5. 9.2.2.5 Dead Time Resistor
        6. 9.2.2.6 Gate Driver Losses
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Examples
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • HBX|48
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.2.4 Gate Resistor

The TPS7H6003-SP has split outputs, allowing for resistors to be placed in series with the gate of the GaN FET in both the turn-on and turn-off paths. These gate resistors serve to dampen ringing at the gate of the device that is caused by parasitic capacitances and inductances. Ringing and noise can also be present due to the high voltage and current switching in the gate drive power loop. This is particularly important for GaN devices which have low values for the absolute maximum gate voltages. Furthermore, the gate resistors can also be used to tune the drive strength of the drive. This is done by limiting the peak current capability of the driver. For this design, 2 Ω resistors are used for both the turn-on and turn-off gate paths. From these values, the high-side peak pull-up current can be calculated as shown in :

Equation 13. IOHH=MIN1.3 A, VBP5HRHOH+RGATE_ON+RGFET(int)

where:

  • VBP5H is the output voltage of the high side linear regulator
  • RHOH is the internal high-side pull-up resistance (1.3 Ω calculated from the high-level output voltage specification)
  • RGATE_ON is the gate resistor value used in the turn-on path
  • RGFET(int) is the internal gate resistance of the GaN FET being driven (typically available from the GaN FET manufacturer)

Note that as indicated in the Specifications section, the peak source current the driver is capable of providing is approximately 1.3 A (typical), so IOHH is limited by this value. In this instance:

Equation 14. IOHH=VBP5HRHOH+RGATE_ON+RGFET(int)=5 V1.3 Ω+2 Ω+0.4 Ω≈1.3 A

Likewise, for the peak high-side sink current:

Equation 15. IOLH=MIN2.5 A, VBP5HRHOL+RGATE_OFF+RGFET(int)

where:

  • RHOL is the internal high-side pull-down resistance (0.07 Ω calculated from the low-level output voltage specification)
  • RGATE_OFF is the gate resistor value used in the turn-off path

As such, the peak sink current can be caluclated as:

Equation 16. IOLH=VBP5HRHOL+RGATE_OFF+RGFET(int)=5 V0.07 Ω+2 Ω+0.4 Ω=2.0 A

The equations for the low-side peak source and sink current are provided, but note that in this instance these are identical to the high-side values calculated.

Equation 17. IOHL=MIN1.3 A, VBP5LRLOH+RGATE_ON+RGFET(int)=5 V1.3 Ω+2 Ω+0.4 Ω≈1.3 A
Equation 18. IOLL=MIN1.3 A, VBP5LRLOL+RGATE_OFF+RGFET(int)=5 V0.07 Ω+2 Ω+0.4 Ω=2.0 A

The selection of the external gate resistor typically requires tuning and is an iterative process. The best practice is to evaluate the value of the gate resistors on the specific PCB design to verify the intended impact and adjust as needed.