Though enhancement mode GaN FETs do not contain a body diode like silicon FETs, the devices are capable of reverse conduction due to the symmetrical device structure. During the reverse conduction periods, the source-drain voltage of the GaN FET is typically higher than what is encountered with a traditional silicon FET, largely depending on the type of GaN device that is being used. As such, the switch node pins of the driver (ASW and PSW, collectively referred to as SW) have a negative voltage present. This negative transient can lead to an excessive bootstrap voltage, since BOOT is always referenced to SW. Furthermore, the printed circuit board layout and device parasitic inductances can further intensify the negative voltage transients. Operating at a bootstrap voltage above the absolute maximum of 16 V can be detrimental to the gate driver, so care must be taken to make sure that the maximum BOOT to SW voltage differential is not exceeded. Generally, BOOT follows SW instantaneously so that the BOOT to SW voltage does not overshoot significantly. However, an external Zener diode can be used between BOOT and SW to clamp the bootstrap voltage to acceptable values during operation.