SNOSDH4 June   2024 TPS7H6005-SEP , TPS7H6015-SEP , TPS7H6025-SEP

ADVMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Device Options Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Quality Conformance Inspection
    8. 7.8 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Input Voltage
      2. 8.3.2  Linear Regulator Operation
      3. 8.3.3  Bootstrap Operation
        1. 8.3.3.1 Bootstrap Charging
        2. 8.3.3.2 Bootstrap Capacitor
        3. 8.3.3.3 Bootstrap Diode
        4. 8.3.3.4 Bootstrap Resistor
      4. 8.3.4  High-Side Driver Startup
      5. 8.3.5  Inputs and Outputs
      6. 8.3.6  Dead Time
      7. 8.3.7  Input Interlock Protection
      8. 8.3.8  Undervoltage Lockout and Power Good (PGOOD)
      9. 8.3.9  Negative SW Voltage Transients
      10. 8.3.10 Level Shifter
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Bootstrap and Bypass Capacitors
        2. 9.2.2.2 Bootstrap Diode
        3. 9.2.2.3 BP5x Overshoot and Undershoot
        4. 9.2.2.4 Gate Resistor
        5. 9.2.2.5 Dead Time Resistor
        6. 9.2.2.6 Gate Driver Losses
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Examples
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DCA|56
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics

Specifications are over ambient temperature operating range TA = –55°C to 125°C, VIN = 10V to 14V, VBP5L = VBP5H = 5V, and no load on LOH, LOL, HOH, and HOL (unless otherwise noted).
PARAMETER TEST CONDITIONS SUBGROUP(1) MIN TYP MAX UNIT
SUPPLY CURRENTS
IQLS Low-side quiescent current  VIN = 12V, BOOT = 10V MODE = PWM, EN = 0V 1, 2, 3 5 6.8 mA
MODE = IIM, LI = HI = 0V 1, 2, 3 5 8
IQHS High-side quiescent current  VIN = 12V, BOOT = 10V MODE = PWM, EN = 0V 1, 2, 3 4 6.3 mA
MODE = IIM, LI = HI = 0V 1, 2, 3 4 6.3
IQBG BOOT to AGND quiescent current (TPS7H6005) SW = 100V, BOOT = 110V 20 µA
IQBG BOOT to AGND quiescent current (TPS7H6015) SW = 28V, BOOT = 38V 15 µA
IQBG BOOT to AGND quiescent current (TPS7H6025) SW = 12V, BOOT = 22V 10 µA
IOP_BG BOOT to AGND operating current (TPS7H6005) SW = 100V, BOOT = 110V 20 µA
IOP_BG BOOT to AGND operating current (TPS7H6015) SW = 28V, BOOT = 38V 15 µA
IOP_BG BOOT to AGND operating current (TPS7H6025) SW = 12V, BOOT = 22V 10 µA
IOP_LS Low-side operating current MODE = PWM, no load for LOL and LOH  f = 500kHz 1, 2, 3 6 9 mA
f = 1MHz 1, 2, 3 8 11
f = 2MHz 1, 2, 3 12 16
f = 5MHz 1, 2, 3 20 30
MODE = IIM, no load for LOL and LOH f = 500kHz 1, 2, 3 6 9
f = 1MHz 1, 2, 3 8 12
f = 2MHz 1, 2, 3 11 17
f = 5MHz 1, 2, 3 20 30
IOP_HS High-side operating current MODE = PWM, no load for HOL and HOH f = 500kHz 1, 2, 3 5 6.5 mA
f = 1MHz 1, 2, 3 5.3 8
f = 2MHz 1, 2, 3 7 10.5
f = 5MHz 1, 2, 3 13 19
MODE = IIM, no load for HOL and HOH f = 500kHz 1, 2, 3 4.5 6.5
f = 1MHz 1, 2, 3 5.3 8
f = 2MHz 1, 2, 3 7 10.5
f = 5MHz 1, 2, 3 11.7 15
LOW-SIDE TO HIGH-SIDE CAPACITANCE
Low-side to high-side capacitance Low-side pins shorted together and high-side pins shorted together 6 pF
GATE DRIVER
VOL Low-level output voltage IOL = 100mA 1, 2, 3 0.07 0.15 V
BP5x – VOH High-level output voltage IOH = 100mA 1, 2, 3 0.13 0.3 V
IOH Peak source current HOH, LOH = 0V, BP5x = 5V 1, 2, 3 0.7 1.3 2.3 A
IOL Peak sink current HOL, LOL = 5V, BP5x = 5V 1, 2, 3 1.6 2.5 4.6 A
INTERNAL REGULATORS
VBP5L Low-side 5V regulator output voltage CBP5L = 1µF 1, 2, 3 4.75 5.0 5.175 V
Required BP5L output capacitor (2) 1, 2, 3 1 µF
VBP5H High-side 5V regulator output voltage CBP5H = 1µF 1, 2, 3 4.75 5.0 5.175 V
Required BP5H output capacitor (2) 1 µF
VBP7L 7V regulator output voltage 1, 2, 3 6.65 7 7.35 V
Required BP7L output capacitor (2) 1 µF
UNDERVOLTAGE PROTECTION
BP5HR BP5H UVLO rising threshold CBP5H = 1µF 1, 2, 3 4.0 4.25 4.5 V
BP5HF BP5H UVLO falling threshold  CBP5H = 1µF 1, 2, 3 3.8 4.05 4.3 V
BP5HH BP5H UVLO hysteresis CBP5H = 1µF 0.2 V
BP5LR BP5L UVLO rising threshold CBP5L = 1µF 1, 2, 3 4.0 4.25 4.5 V
BP5LF BP5L UVLO falling threshold  CBP5L = 1µF 1, 2, 3 3.8 4.05 4.3 V
BP5LH BP5L UVLO hysteresis CBP5L = 1µF 0.2 V
BP7LR BP7L UVLO rising threshold CBP7L = 1µF 1, 2, 3 6.2 6.5 6.8 V
BP7LF BP7L UVLO falling threshold  CBP7L = 1µF 1, 2, 3 5.9 6.2 6.5 V
BP7LH BP7L UVLO hysteresis CBP7L = 1µF 0.3 V
VINR VIN UVLO rising threshold 1, 2, 3 8.0 8.6 9.0 V
VINF VIN UVLO falling threshold 1, 2, 3 7.5 8.1 8.5 V
VINH VIN UVLO hysteresis 0.5 V
BOOTR BOOT UVLO rising threshold 1, 2, 3 6.6 7.1 7.4 V
BOOTF BOOT UVLO falling threshold 1, 2, 3 6.2 6.65 7 V
BOOTH BOOT UVLO hysteresis 0.45 V
INPUT PINS
VIR Input rising edge threshold 1, 2, 3 1.80 2.65 V
VIF Input falling edge threshold 1, 2, 3 1.15 1.85 V
VIHYS Input hysteresis 0.8 V
RPD Input pull-down resistance V = 2.15V applied at input (EN_HI or PWM_LI) 1, 2, 3 100 400 kΩ
PROGRAMMBLE DEAD TIME
TDLH LO off to HO on dead time MODE = PWM, LO falling to HO rising (90% to 10%), f ≤ 2MHz RLH = 3.32kΩ 9, 10 , 11 0 4.5 10 ns
RLH = 11.8kΩ 9, 10 , 11 8 12 15.5
RLH = 21kΩ 9, 10 , 11 15.5 21 24
RLH = 52.3kΩ 9, 10 , 11 36 50 59
RLH = 105kΩ 9, 10 , 11 74 97 113.5
TDHL HO off to LO on dead time MODE = PWM, HO falling to LO rising (90% to 10%), f ≤ 2MHz RHL = 7.87kΩ 9, 10 , 11 0 5 10 ns
RHL = 13.3kΩ 9, 10 , 11 6 10.5 14
RHL = 23.7kΩ 9, 10 , 11 16 21 24.5
RHL = 57.6kΩ 9, 10 , 11 44 53 61
RHL = 113kΩ 9, 10 , 11 86 105 125
BOOTSTRAP DIODE SWITCH
RBST_SW Bootstrap diode switch resistance IBST_SW = 100mA 1, 2, 3 0.43 Ω
Bootstrap diode switch parallel resistance IBST_RP = 1mA 1, 2, 3 0.8 1 1.2 kΩ
POWER GOOD
Logic-low output IFLT = 1mA 1, 2, 3 0.4 V
PGOOD internal resistance BP5L = 5V, BP7L = 7V, VIN = 12V 1, 2, 3 0.7 1 1.9 MΩ
Minimum BP5L voltage for valid PGOOD output 1, 2, 3 2 2.45 V
(1) Subgroups are applicable for QML parts.  For subgroup definitions, see Quality Conformance Inspection.
(2) Specified by design; not tested in production.