SBVS445A October   2024  – December 2024 TPS7N53

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Output Voltage Setting and Regulation
      2. 6.3.2 Low-Noise, Ultra-High Power-Supply Rejection Ratio (PSRR)
      3. 6.3.3 Programmable Soft-Start (SS Pin)
      4. 6.3.4 Precision Enable and UVLO
      5. 6.3.5 Power-Good Pin (PG Pin)
      6. 6.3.6 Active Discharge
      7. 6.3.7 Thermal Shutdown Protection (TSD)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation
      2. 6.4.2 Disabled
      3. 6.4.3 Current-Limit Operation
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1  Precision Enable (External UVLO)
      2. 7.1.2  Input and Output Capacitor Requirements (CIN and COUT)
      3. 7.1.3  Recommended Capacitor Types
      4. 7.1.4  Soft-Start (SS Pin) and Noise Reduction (NR Pin)
      5. 7.1.5  Charge Pump Noise
      6. 7.1.6  Optimizing Noise and PSRR
      7. 7.1.7  Adjustable Operation
      8. 7.1.8  Load Transient Response
      9. 7.1.9  Power-Good Functionality
      10. 7.1.10 Paralleling for Higher Output Current and Lower Noise
      11. 7.1.11 Power Dissipation (PD)
      12. 7.1.12 Estimating Junction Temperature
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Package Option Addendum

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.1 Overview

The TPS7N53 is a low-noise (2.2μVRMS over 100Hz to 100kHz bandwidth), ultra-high PSRR (> 33dB to 1MHz), high-accuracy (1.5%), ultra-low-dropout (LDO) linear voltage regulator with an input range of 1.1V to 2V and an output voltage range from 0.5V to 1.5V. This device uses innovative circuitry to achieve wide bandwidth and high loop gain, resulting in ultra-high PSRR even with very low operational headroom [VOpHr = (VIN – VOUT)]. The TPS7N53 has an integrated charge-pump for ease of use to allow low dropout. At a high level, the device has two main primary features (the current reference and the unity-gain LDO buffer) and a few secondary features (such as the adjustable soft-start inrush control, precision enable, and PG pin).

The current reference is controlled by the REF pin. This pin sets the output voltage with a single resistor.

The SS pin sets the start-up time, and the NR filters the noise generated by the reference and external set resistor.

The unity-gain LDO buffer controls the output voltage. The low noise does not increase with output voltage and provides wideband PSRR. As such, the SNS pin is only used for remote sensing of the load.

The low-noise current reference, 150μA typical, is used in conjunction with an external resistor (RREF) to set the output voltage. This process allows the output voltage range to be set from 0.5V to 1.5V. To achieve low noise and allow for a soft-start inrush, external capacitors, CNR and CSS(typically 1μF and 10nF), are placed on the NR and SS pins. When start-up is completed and the switch between REF and NR is closed, the CNR capacitor is in parallel with the RREF resistor attenuating the band-gap noise. The RREF resistor sets the output voltage. This unity-gain LDO provides ultra-high PSRR over a wide frequency range without compromising load and line transients.

The EN pin sets the precision enable feature; a resistor divider on this pin selects the optimal input voltage at which the device starts. There are two independent undervoltage lockout (UVLO) voltages in this device: the internal fixed UVLO thresholds for the IN, and the externally adjustable UVLO threshold using the EN pin.

This regulator offers current limit, thermal protection, is fully specified from –40°C to +125°C, and is offered in a 16-pin WQFN, 3-mm × 3-mm thermally efficient package.