SBVS445A October   2024  – December 2024 TPS7N53

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Output Voltage Setting and Regulation
      2. 6.3.2 Low-Noise, Ultra-High Power-Supply Rejection Ratio (PSRR)
      3. 6.3.3 Programmable Soft-Start (SS Pin)
      4. 6.3.4 Precision Enable and UVLO
      5. 6.3.5 Power-Good Pin (PG Pin)
      6. 6.3.6 Active Discharge
      7. 6.3.7 Thermal Shutdown Protection (TSD)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation
      2. 6.4.2 Disabled
      3. 6.4.3 Current-Limit Operation
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1  Precision Enable (External UVLO)
      2. 7.1.2  Input and Output Capacitor Requirements (CIN and COUT)
      3. 7.1.3  Recommended Capacitor Types
      4. 7.1.4  Soft-Start (SS Pin) and Noise Reduction (NR Pin)
      5. 7.1.5  Charge Pump Noise
      6. 7.1.6  Optimizing Noise and PSRR
      7. 7.1.7  Adjustable Operation
      8. 7.1.8  Load Transient Response
      9. 7.1.9  Power-Good Functionality
      10. 7.1.10 Paralleling for Higher Output Current and Lower Noise
      11. 7.1.11 Power Dissipation (PD)
      12. 7.1.12 Estimating Junction Temperature
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Package Option Addendum

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Electrical Characteristics

over operating temperature range (TJ = –40 °C to +125 °C), VIN(NOM) = VOUT(NOM) + 0.4V, IOUT = 0A, VEN = 1.8V, CIN  = 10 µF, COUT =10μF, CNR = open, CSS = 10nF, SNS pin shorted to OUT pin, and PG pin pulled up to VIN with 100 kΩ (unless otherwise noted); typical values are at TJ = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VUVLO(IN) Input supply UVLO VIN rising 1.07 1.1 V
VHYS(UVLO_IN) Input supply UVLO hysteresis 60 mV
ISS SS fast start-up charging current VSS = GND, VIN = 1.1 V 27 30 35 µA
tSS Soft-Start Time CSS = 10nF, VOUT = 0.75V  0.7 ms
VOUT Output voltage accuracy (1) 0.5V ≤ VOUT ≤ 1.5V,
0A ≤ IOUT ≤ 3A,
1.1V ≤ VIN ≤ 2.2V		 –1.5 ±0.5 1.5 %
IREF REF current pin VIN = 1.1 V, VOUT = 0.5 V, ILOAD = 0 A 150 µA
1.1V ≤ VIN ≤ 2.2V (1), 0.5V ≤ VOUT ≤ 1.5V,
0A ≤ IOUT ≤ 3A		 –1.5 ±1 1.5 %
VOS Output offset voltage (VNR - VOUT) 1.1V ≤ VIN ≤ 2.2V (1), 0.5 V ≤ VOUT ≤ 1.5V,
0A ≤ IOUT ≤ 3A		 –2 2 mV
ΔVOUT(ΔVIN) Line regulation 1.1V ≤ VIN ≤ 2.2V, VOUT = 0.5V, IOUT = 0A -200 µV/V
ΔVOUT(ΔIOUT) Load regulation VOUT = 1.5V, 0A ≤ IOUT ≤ 3A -100 µV/A
VDO Dropout voltage (2) VOUT  ≥ 1.2V, IOUT = 3A 95 140 mV
VOUT  ≥ 1.2V, IOUT = 3A, –40°C ≤ TJ ≤ +85°C 125
ILIM Output current limit VOUT forced at 0.9 × VOUT(NOM),
VOUT(NOM) = 1.5V,
VIN = VOUT(NOM) + 400 mV		 3.3 3.6 3.9 A
ISC Short circuit current limit RLOAD = 10 mΩ, under foldback operation 1.1 A
IGND GND pin current IOUT = 3 A, VOUT = 1.5V
 		 15 mA
VIN = 1.1 V, IOUT = 3 A, VOUT = 0.5 V 13 15 19
ISDN Shutdown GND pin current PG = (open), VIN = 2.2 V, VEN = 0.4 V 100 300 µA
IEN EN pin current VIN = 2.2V, 0 V ≤ VEN ≤ 6 V -5 5 µA
VIH(EN) EN trip point rising (turn-on) VIN = 1.1 V 0.62 0.65 0.68 V
VIL(EN) EN trip point falling (turn-off) VIN = 1.1 V 0.58 0.61 0.64 V
VHYS(EN) EN trip point hysteresis VIN = 1.1 V 40 mV
VIT(PG) PG pin threshold For PG transitioning low with falling VOUT, VIN = 1.1 V,
VOUT < VIT(PG), IPG = –1 mA (current into device)		 87 90 93 %
VHYS(PG) PG pin hysteresis VIN = 1.1 V, VOUT < VIT(PG),
IPG = –1 mA (current into device)		 2 %
VOL(PG) PG pin low-level output voltage VIN = 1.1 V, VOUT < VIT(PG),
IPG = –1 mA (current into device)		 0.4 V
ILKG(PG) PG pin leakage current VPG = 6 V, VOUT > VIT(PG), VIN = 1.1 V 1 µA
PSRR Power-supply ripple rejection f = 1 MHz, VIN = 1.8V, VOUT(NOM) = 1.5 V, IOUT = 3 A, CNR = 1 µF 23 dB
f = 1 MHz, VIN =1.1 V, VOUT(NOM) = 0.5 V, IOUT = 3 A, CNR = 1 µF 25
Vn Output noise voltage BW = 10Hz to 100kHz,
1.1V ≤ VIN ≤ 2.2 V, 0.5V ≤ VOUT ≤ 1.5V,
IOUT = 3A, CNR = 1 µF		 8 µVRMS
Vn Output noise voltage BW = 100Hz to 100kHz,
1.1V ≤ VIN ≤ 2.2V, 0.5V ≤ VOUT ≤1.5V,
IOUT = 3A, CNR = 1µF		 2.2 µVRMS
RDIS Output pin active discharge resistance VIN = 1.1V, VEN = 0V VOUT = 0.2V 110 Ω
RNR_DIS NR pin active discharge resistance VIN = 1.1 V, VEN = 0 V, VNR = 0.2V 250 Ω
RSS_DIS SS pin active discharge resistance VIN = 1.1V, VEN = 0V, VSS = 0.2V 5.6 kΩ
TSD(shutdown) Thermal shutdown temperature Shutdown, temperature increasing 165 °C
TSD(reset) Thermal shutdown reset temperature Reset, temperature decreasing 150 °C
(1) Limited by max power dissipation of 2 W.
(2) VREF = VIN, VSNS = 95% × VREF.