SLVSAZ9D June   2012  – February 2018 TPS81256

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application
      2.      Efficiency vs Load Current
  4. 4 Revision History
  5. 5 Device Options
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Operation
      2. 8.3.2 Power-Save Mode
      3. 8.3.3 Current Limit Operation, Maximum Output Current
    4. 8.4 Device Functional Modes
      1. 8.4.1 Softstart, Enable
      2. 8.4.2 Load Disconnect and Reverse Current Protection
      3. 8.4.3 Undervoltage Lockout
      4. 8.4.4 Thermal Regulation
      5. 8.4.5 Thermal Shutdown
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Output Capacitor Selection CEXT
        2. 9.2.2.2 Input Capacitor Selection
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Surface Mount Information
    4. 11.4 Thermal and Reliability Information
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • SIP|9
Thermal pad, mechanical data (Package|Pins)
Orderable Information

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

MicroSiP DC/DC Module Package Dimensions

The TPS81256 device is available in a 9-bump ball grid array (BGA) package. The package dimensions are:

TPS81256 POs_top_bot_lvsaz9.gif
Code:
  • CC — Package marking Chip Code (see Package Option Addendum for more details)
  • YML — Y: Year, M: Month, L: Lot trace code
  • LSB — L: Lot trace code, S: Site code, B: Board locator
Figure 27. µSIP 9-Pin Dimensions and Markings
TPS81256 SIP0009A_4218355_Page_01.gif
TPS81256 SIP0009A_4218355_Page_02.gif
TPS81256 SIP0009A_4218355_Page_03.gif