SNVSBZ6 May 2021 TPS92380 , TPS92381
PRODUCTION DATA
In SEPIC mode the maximum voltage at the SW pin is equal to the sum of the input voltage and the output voltage. Because of this, the maximum sum of input and output voltage must be limited below 49 V. See the Detailed Design Procedure section for general external component guidelines. Main differences of SEPIC compared to boost are described below.
Power Stage Designerâ„¢ Tool can be used for modeling SEPIC behavior. For detailed explanation on SEPIC see Texas Instruments Analog Applications Journal Designing DC/DC Converters Based on SEPIC Topology.