VCCx, VIN |
VCCx |
VCCx Voltage |
VVIN = 40 V or VVIN = 65 V, 0 A ≤ External Load ≤ 500 µA |
6.9 |
7.5 |
8.25 |
V |
VCCx2 |
VCCx Voltage with External Load |
External Load = 500 µA |
6.9 |
7.5 |
8.25 |
V |
VCCx_UVLO |
VCCx undervoltage lockout |
Falling threshold, VVIN = 10 V |
5.65 |
5.9 |
6.1 |
V |
VCCx_UVHYS |
VCCx undervoltage lockout Hysteresis |
|
|
0.25 |
|
V |
IVCCx-LIM |
VCCx regulator current limit |
VCC shorted to GND. |
25 |
38 |
48 |
mA |
IVIN |
Operating Current |
Not Switching |
|
3 |
4 |
mA |
VDO |
LDO drop-out voltage |
IVCC = 5 mA, VVIN = 5 V |
|
90 |
225 |
mV |
Peak Current Comparator (CSPx, CSNx) |
VCSTx |
VCSPx-VCSNx peak current threshold |
LEDx_PKTH_DAC = 255 |
245 |
255 |
265 |
mV |
LEDx_PKTH_DAC = 127 |
118.5 |
127 |
135.5 |
mV |
LEDx_PKTH_DAC = 10 |
|
10 |
|
mV |
ICSN |
CSN input bias current |
|
|
0.4 |
1.5 |
µA |
tDEL |
CSN pin falling delay |
CSNx fall to GATEx fall (1V/us stimulus) |
|
58 |
110 |
ns |
tLEB |
Leading edge blanking (minimum on-time) |
Minimum Pulse Width |
165 |
200 |
235 |
ns |
CSPUVLO |
CSPx UVLO Falling Threshold |
|
4.65 |
4.90 |
5.15 |
V |
CSPUVLO-H |
CSPx UVLO Hysteresis |
|
|
520 |
|
mV |
Gate Drivers (GATEx, SWx and BOOTx) |
RDSP |
GATEx PFET ( RDS High ) |
|
|
7.3 |
|
Ω |
RDSN |
GATEx NFET ( RDS Low ) |
|
|
2.8 |
|
Ω |
VBOOT-UVLO |
Voltage where gate drive is disabled |
VBOOT to VSW , VBOOT falling |
3.6 |
4.4 |
5.2 |
V |
VBOOT-UVLO-HYS |
Hysteresis on BOOTx UVLO |
VBOOTx to VSWx |
|
200 |
|
mV |
IPD PWMx |
Pull down from SWx when PWMx Low |
PWMx low, (BOOTx to SWx) = 5V, VSWx= 8V |
|
200 |
260 |
µA |
IPD BOOTx |
VBOOTx -VSWx < VBOOT-UVLO |
PWMx high, (BOOTx to SWx) < BOOT_UVLO, VSWx = 8 V |
|
5 |
7 |
mA |
IBOOT_Q |
BOOTx quiescent current |
(BOOTx to SWx) = 5.5 V, 0 V ≤ VSWx ≤ 65 V |
|
100 |
200 |
µA |
OFF-TIMER |
tOFF |
Off-time |
VLEDx = 30 V, tOFFXDAC = 255 |
3.2 |
4.1 |
4.8 |
µs |
tD-OFF |
COFF threshold to gate rising delay |
Specified by design |
|
50 |
|
ns |
tOFF-MAX |
Maximum off-time |
tOFF-MAXDAC = 255 |
|
65 |
|
µs |
Enable and Input UVLO |
VEN/UV1 |
EN/UV pin threshold |
EN/UV pin rising |
1.18 |
1.24 |
1.30 |
V |
VEN/UV-HYS1 |
EN/UV pin hysteresis |
Difference between rising and falling threshold |
|
100 |
|
mV |
tEN/UV1 |
EN/UV pin delay |
EN/UV pin rising to GATEx pin rising. LEDx_MAXOFF_DAC = 0 |
|
300 |
|
ns |
EN/UV pin falling to GATEx pin falling |
|
470 |
|
ns |
IEN/UV-HYST1 |
EN/UV Hysteresis Current |
EN/UV = 2 V |
12 |
16 |
28 |
µA |
VEN/UV2 |
EN/UV LED1_EN and LED2_EN override threshold |
EN/UV pin rising writes LED1_EN and LED2_EN = 1 |
|
23.4 |
|
V |
VEN/UV-HYS2 |
EN/UV pin hysteresis |
Difference between rising and falling threshold |
|
3 |
|
V |
tEN/UV2 |
EN/UV pin delay 2 |
EN/UV pin rising to GATEx pin rising. LEDx_MAXOFF_DAC = 0 |
|
520 |
|
ns |
PWM, MOSI, SCK, SSN |
ILKG |
Leakage current |
|
|
|
1 |
µA |
VIL |
Low level input voltage threshold |
|
0.8 |
|
|
V |
VIH |
High level input voltage threshold |
|
|
|
1.8 |
V |
tPWM |
PWM pin delay |
PWM pin rising to GATE pin rising |
|
68 |
105 |
ns |
PWM pin falling to GATE pin falling |
|
55 |
100 |
ns |
MISO |
VOL |
MISO low, IMISO applied |
IMISO = 10 mA |
|
0.26 |
0.51 |
V |
RDS |
MISO Pull-down resistance |
IMISO = 10 mA |
|
26 |
|
Ω |
ADC |
ADCTEMP |
ADC Reading T = –40°C |
|
|
104 |
|
Code |
ADC Reading T = 25°C |
|
|
130 |
|
Code |
ADC Reading T= 150°C |
|
|
171 |
|
Code |
ADCLEDx |
ADC Reading VLEDx= 60 V |
|
226 |
230 |
240 |
Code |
ADC Reading VLEDx = 10 V |
|
37 |
38 |
39 |
Code |
ADC Reading VLEDx = 1 V |
|
2 |
3 |
4 |
Code |
SPI Interface |
tSS_SU |
SSN Setup Time |
Falling edge of SSN to 1st SCK rising edge |
500 |
|
|
ns |
tSS_H |
SSN Hold Time |
Falling edge of 16th SCK to SSN rising edge |
250 |
|
|
ns |
tSCK |
SCK Period |
Clock period |
500 |
|
|
ns |
DSCK |
SCK Duty Cycle |
Clock duty cycle |
40 |
|
60 |
% |
tSU |
MOSI Setup Time |
MOSI valid to rising edge SCK |
250 |
|
|
ns |
tH |
MOSI Hold Time |
MOSI valid after rising edge SCK |
275 |
|
|
ns |
tHI_Z |
MISO Tri-State Time |
Time to tri-state (deactivate low-side switch) MISO after SSN rising edge |
110 |
|
320 |
ns |
tMISO_HL |
MISO Valid High-to-Low |
Time to place valid "0" on MISO after falling SCK edge |
|
|
320 |
ns |
tMISO_LH |
MISO Valid Low-to-High |
Time to tri-state (deactivate the internal low-side switch) MISO after falling SCK edge. tRC is the time added by the application total capacitance and resistance. |
|
|
320+tRC |
ns |
tZO_HL |
MISO Drive Time High-to-Low |
SSN Falling Edge to MISO Falling |
|
|
320 |
ns |
tSS |
SSN High Time |
How long SSN must remain high between transactions |
1000 |
|
|
ns |
THERMAL SHUTDOWN |
TSD |
Thermal shutdown temperature |
|
|
175 |
|
°C |
TSD HYST |
Thermal shutdown hysteresis |
|
|
10 |
|