SLUSCZ1 May   2017 TPS92518-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 CSN Pin Falling Delay (tDEL)
    2. 7.2 Off-Timer (tOFF)
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  General Operation
        1. 8.3.1.1 Constant Off-Time vs. Constant µs×V operation
        2. 8.3.1.2 Output Equation
        3. 8.3.1.3 OFF Timer
          1. 8.3.1.3.1 Off-time and Maximum Off-time Calculations
      2. 8.3.2  Important System Considerations: Off-Timer and Maximum Peak Threshold Values
        1. 8.3.2.1 Peak Current Sense Comparator
        2. 8.3.2.2 Peak Current Threshold - LEDx _PKTH_DAC
        3. 8.3.2.3 Off-Time Thresholds - LEDx_TOFF_DAC and LEDx_MAXOFF_DAC
      3. 8.3.3  Shunt FET or Matrix dimming: Maximum Off-timer Calculation
        1. 8.3.3.1 Output Ringing and TPS92518-Q1 Protection
        2. 8.3.3.2 Live Peak and Off-Time Threshold Changes
      4. 8.3.4  VIN and the VCC Internal Regulators
      5. 8.3.5  Output Enable Control Logic
        1. 8.3.5.1 EN/UV2 - SPI Control Bypass
      6. 8.3.6  BOOT Capacitor and BOOT UVLO
      7. 8.3.7  Drop-out Operation
        1. 8.3.7.1 Early Drop-Out (Boot Capacitor Voltage >> VBOOT-UVLO)
        2. 8.3.7.2 Full Drop-Out (Boot Capacitor Voltage reaching VBOOT-UVLO)
        3. 8.3.7.3 Minimum BOOT Voltage and FET Control
        4. 8.3.7.4 BOOT Controlled internal Pull-Down
      8. 8.3.8  Analog and PWM Dimming
        1. 8.3.8.1 Dimming Methods
        2. 8.3.8.2 PWMx Pin Operation
        3. 8.3.8.3 PWM Dimming - Current Rise Performance
        4. 8.3.8.4 PWM and Analog Dimming - Linearity Limitations and Buck Converters
          1. 8.3.8.4.1 PWM:
          2. 8.3.8.4.2 ANALOG:
        5. 8.3.8.5 DCM Current Calculation
        6. 8.3.8.6 Current Sharing
      9. 8.3.9  VIN and CSPx Pin Configuration
      10. 8.3.10 Enable and Undervoltage Lock-out Configuration
      11. 8.3.11 Voltage Sampling and DAC Operation
        1. 8.3.11.1 ADC Control and LED Voltage Updating
      12. 8.3.12 Device Functional Modes
        1. 8.3.12.1 Analog Dimming
        2. 8.3.12.2 PWM Dimming
    4. 8.4 Serial Interface
      1. 8.4.1 Command Frame
      2. 8.4.2 Response Frame Formats
        1. 8.4.2.1 Read Response Frame Format
        2. 8.4.2.2 Write Response Frame Format
        3. 8.4.2.3 Write Error/POR Frame Format
        4. 8.4.2.4 SPI Error
    5. 8.5 Registers
      1. 8.5.1  CONTROL Register (Address = 00h) [reset = 00h]
        1. Table 3. CONTROL Register Field Descriptions
      2. 8.5.2  STATUS (FAULT) Register (Address = 01h) [reset = 10h]
        1. Table 4. STATUS Register Field Descriptions
      3. 8.5.3  THERM_WARN_LMT Register (Address = 02h) [reset = 80h]
        1. Table 5. THERM_WARN_LMT Register Field Descriptions
      4. 8.5.4  LED1_PKTH_DAC Register (Address = 03h) [reset = 80h]
        1. Table 6. LED1_PKTH_DAC Register Field Descriptions
      5. 8.5.5  LED2_PKTH_DAC Register (Address = 04h) [reset = 80h]
        1. Table 7. LED2_PKTH_DAC Register Field Descriptions
      6. 8.5.6  LED1_TOFF_DAC Register (Address = 05h) [reset = 80h]
        1. Table 8. LED1_TOFF_DAC Register Field Descriptions
      7. 8.5.7  LED2_TOFF_DAC Register (Address = 06h) [reset = 80h]
        1. Table 9. LED2_TOFF_DAC Register Field Descriptions
      8. 8.5.8  LED1_MAXOFF_DAC Register (Address = 07h) [reset = 80h]
        1. Table 10. LED1_MAXOFF_DAC Register Field Descriptions
      9. 8.5.9  LED2_MAXOFF_DAC Register (Address = 08h) [reset = 80h]
        1. Table 11. LED2_MAXOFF_DAC Register Field Descriptions
      10. 8.5.10 VTHERM Register (Address = 09h) [reset = 0h]
        1. Table 12. VTHERM Register Field Descriptions
      11. 8.5.11 LED1_MOST_RECENT Register (Address = 0Ah) [reset = 0h]
        1. Table 13. LED1_MOST_RECENT Register Field Descriptions
      12. 8.5.12 LED1_LAST_ON Register (Address = 0Bh) [reset = 0h]
        1. Table 14. LED1_LAST_ON Register Field Descriptions
      13. 8.5.13 LED1_LAST_OFF Register (Address = 0Ch) [reset = 0h]
        1. Table 15. LED1_LAST_OFF Register Field Descriptions
      14. 8.5.14 LED2_MOST_RECENT Register (Address = 0Dh) [reset = 0h]
        1. Table 16. LED2_MOST_RECENT Register Field Descriptions
      15. 8.5.15 LED2_LAST_ON Register (Address = 0Eh) [reset = 0h]
        1. Table 17. LED2_LAST_ON Register Field Descriptions
      16. 8.5.16 LED2_LAST_OFF Register (Address = 0Fh) [reset = 0h]
        1. Table 18. LED2_LAST_OFF Register Field Descriptions
      17. 8.5.17 Reset Register (Address = 10h) [reset = 0h]
        1. Table 19. Reset Register Field Descriptions
    6. 8.6 Programming
      1. 8.6.1 TPS92518-Q1 Register Typedef - Sample Code
      2. 8.6.2 Command Frame - Sample Code
      3. 8.6.3 SPI Read/Write - Sample Code
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Dos and Don'ts
  10. 10Power Supply Recommendations
    1. 10.1 Input Source Direct from Battery
    2. 10.2 Input Source from a Boost Stage
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

VVIN = 14 V, -40 °C ≤ TJ ≤ 150 °C, unless otherwise specified
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VCCx, VIN
VCCx VCCx Voltage VVIN = 40 V or VVIN = 65 V, 0 A ≤ External Load ≤ 500 µA 6.9 7.5 8.25 V
VCCx2 VCCx Voltage with External Load External Load = 500 µA 6.9 7.5 8.25 V
VCCx_UVLO VCCx undervoltage lockout Falling threshold, VVIN = 10 V 5.65 5.9 6.1 V
VCCx_UVHYS VCCx undervoltage lockout Hysteresis 0.25 V
IVCCx-LIM VCCx regulator current limit VCC shorted to GND. 25 38 48 mA
IVIN Operating Current Not Switching 3 4 mA
VDO LDO drop-out voltage IVCC = 5 mA, VVIN = 5 V 90 225 mV
Peak Current Comparator (CSPx, CSNx)
VCSTx VCSPx-VCSNx peak current threshold LEDx_PKTH_DAC = 255 245 255 265 mV
LEDx_PKTH_DAC = 127 118.5 127 135.5 mV
LEDx_PKTH_DAC = 10 10 mV
ICSN CSN input bias current 0.4 1.5 µA
tDEL CSN pin falling delay CSNx fall to GATEx fall (1V/us stimulus) 58 110 ns
tLEB Leading edge blanking (minimum on-time) Minimum Pulse Width 165 200 235 ns
CSPUVLO CSPx UVLO Falling Threshold 4.65 4.90 5.15 V
CSPUVLO-H CSPx UVLO Hysteresis 520 mV
Gate Drivers (GATEx, SWx and BOOTx)
RDSP GATEx PFET ( RDS High ) 7.3 Ω
RDSN GATEx NFET ( RDS Low ) 2.8 Ω
VBOOT-UVLO Voltage where gate drive is disabled VBOOT to VSW , VBOOT falling 3.6 4.4 5.2 V
VBOOT-UVLO-HYS Hysteresis on BOOTx UVLO VBOOTx to VSWx 200 mV
IPD PWMx Pull down from SWx when PWMx Low PWMx low, (BOOTx to SWx) = 5V, VSWx= 8V 200 260 µA
IPD BOOTx VBOOTx -VSWx < VBOOT-UVLO PWMx high, (BOOTx to SWx) < BOOT_UVLO, VSWx = 8 V 5 7 mA
IBOOT_Q BOOTx quiescent current (BOOTx to SWx) = 5.5 V, 0 V ≤ VSWx ≤ 65 V 100 200 µA
OFF-TIMER
tOFF Off-time VLEDx = 30 V, tOFFXDAC = 255 3.2 4.1 4.8 µs
tD-OFF COFF threshold to gate rising delay Specified by design 50 ns
tOFF-MAX Maximum off-time tOFF-MAXDAC = 255 65 µs
Enable and Input UVLO
VEN/UV1 EN/UV pin threshold EN/UV pin rising 1.18 1.24 1.30 V
VEN/UV-HYS1 EN/UV pin hysteresis Difference between rising and falling threshold 100 mV
tEN/UV1 EN/UV pin delay EN/UV pin rising to GATEx pin rising. LEDx_MAXOFF_DAC = 0 300 ns
EN/UV pin falling to GATEx pin falling 470 ns
IEN/UV-HYST1 EN/UV Hysteresis Current EN/UV = 2 V 12 16 28 µA
VEN/UV2 EN/UV LED1_EN and LED2_EN override threshold EN/UV pin rising writes LED1_EN and LED2_EN = 1 23.4 V
VEN/UV-HYS2 EN/UV pin hysteresis Difference between rising and falling threshold 3 V
tEN/UV2 EN/UV pin delay 2 EN/UV pin rising to GATEx pin rising. LEDx_MAXOFF_DAC = 0 520 ns
PWM, MOSI, SCK, SSN
ILKG Leakage current 1 µA
VIL Low level input voltage threshold 0.8 V
VIH High level input voltage threshold 1.8 V
tPWM PWM pin delay PWM pin rising to GATE pin rising 68 105 ns
PWM pin falling to GATE pin falling 55 100 ns
MISO
VOL MISO low, IMISO applied IMISO = 10 mA 0.26 0.51 V
RDS MISO Pull-down resistance IMISO = 10 mA 26 Ω
ADC
ADCTEMP ADC Reading T = –40°C 104 Code
ADC Reading T = 25°C 130 Code
ADC Reading T= 150°C 171 Code
ADCLEDx ADC Reading VLEDx= 60 V 226 230 240 Code
ADC Reading VLEDx = 10 V 37 38 39 Code
ADC Reading VLEDx = 1 V 2 3 4 Code
SPI Interface
tSS_SU SSN Setup Time Falling edge of SSN to 1st SCK rising edge 500 ns
tSS_H SSN Hold Time Falling edge of 16th SCK to SSN rising edge 250 ns
tSCK SCK Period Clock period 500 ns
DSCK SCK Duty Cycle Clock duty cycle 40 60 %
tSU MOSI Setup Time MOSI valid to rising edge SCK 250 ns
tH MOSI Hold Time MOSI valid after rising edge SCK 275 ns
tHI_Z MISO Tri-State Time Time to tri-state (deactivate low-side switch) MISO after SSN rising edge 110 320 ns
tMISO_HL MISO Valid High-to-Low Time to place valid "0" on MISO after falling SCK edge 320 ns
tMISO_LH MISO Valid Low-to-High Time to tri-state (deactivate the internal low-side switch) MISO after falling SCK edge. tRC is the time added by the application total capacitance and resistance. 320+tRC ns
tZO_HL MISO Drive Time High-to-Low SSN Falling Edge to MISO Falling 320 ns
tSS SSN High Time How long SSN must remain high between transactions 1000 ns
THERMAL SHUTDOWN
TSD Thermal shutdown temperature 175 °C
TSD HYST Thermal shutdown hysteresis 10