SLUSEG1A August   2021  – December 2021 TPS92519-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Buck Converter Switching Operation
      2. 7.3.2  Switching Frequency and Adaptive On-Time Control
      3. 7.3.3  Minimum On-Time, Off-Time, and Inductor Ripple
      4. 7.3.4  Enable
      5. 7.3.5  LED Current Regulation and Error Amplifier
      6. 7.3.6  Start-up Sequence
      7. 7.3.7  Analog Dimming and Forced Continuous Conduction Mode
      8. 7.3.8  External PWM Dimming and Input Undervoltage Lockout (UVLO)
      9. 7.3.9  Shunt FET Dimming or Matrix Beam Application
      10. 7.3.10 Bias Supply
      11. 7.3.11 Bootstrap Supply
      12. 7.3.12 Faults and Diagnostics
      13. 7.3.13 Output Short Circuit Fault
      14. 7.3.14 Output Open Circuit Fault
      15. 7.3.15 Parallel Operation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power On Reset (POR)
      2. 7.4.2 Run Mode
      3. 7.4.3 Sleep Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Duty Cycle Consideration
      2. 8.1.2  Switching Frequency Selection
      3. 8.1.3  LED Current Set Point
      4. 8.1.4  Inductor Selection
      5. 8.1.5  Output Capacitor Selection
      6. 8.1.6  Input Capacitor Selection
      7. 8.1.7  Bootstrap Capacitor Selection
      8. 8.1.8  Compensation Capacitor Selection
      9. 8.1.9  Input Undervoltage Protection
      10. 8.1.10 CSN Protection Diode
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Calculating Duty Cycle
        2. 8.2.2.2 Calculating Minimum On-Time and Off-Time
        3. 8.2.2.3 Minimum Switching Frequency
        4. 8.2.2.4 LED Current Set Point
        5. 8.2.2.5 Inductor Selection
        6. 8.2.2.6 Output Capacitor Selection
        7. 8.2.2.7 Bootstrap Capacitor Selection
        8. 8.2.2.8 Compensation Capacitor Selection
        9. 8.2.2.9 PWM Dimming and Input Voltage Protection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Compact Layout for EMI Reduction
        1. 10.1.1.1 Ground Plane
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

Figure 5-1 DAP Package 32-Pin HTSSOP Top View
Table 5-1 Pin Functions
PIN I/O DESCRIPTION
NAME NO.
DAP
BST1 19 P Supply input for high-side MOSFET gate drive circuit. Connect a ceramic capacitor between BSTx and SWx pins. An internal diode is connected between V5D and BSTx.
BST2 30 P
COMP1 16 I/O Output of internal transconductance error amplifier. Connect an integral compensation network to ensure stability.
COMP2 1 I/O
CSN1 17 I Negative input (–) of internal rail-to-rail transconductance error amplifier. Connect directly to the negative node of the LED current sense resistor, RCS.
CSN2 32 I
CSP1 18 I Positive input (+) of internal rail-to-rail transconductance error amplifier. Connect directly to the positive node of the LED current sense resistor, RCS.
CSP2 31 I
EN 24 I An active high logic input enables the devices. Pull this pin low to enter low power sleep state.
FLT1 22 O Open-drain fault indicator. Connect to V5D with a resistor to create an active low fault signal output.
FLT2 27 O
FSET 25 I Frequency select input. Connect to V5D to operate at nominal frequency of 440 kHz. Connect to GND to operate at nominal frequency of 2.1 MHz.
GND 7, 10 G Signal ground. Return for the internal voltage reference and analog circuits. Connect to circuit ground to complete return path.
IADJ1 23 I Analog adjust input. Input below 100 mV disables the channel. The analog input can be varied between 140 mV to 2.4 V to set current reference from 10 mV to 173 mV. Connect a 0.1-μF capacitor from pin to GND.
IADJ2 26 I
PGND 3, 4, 13, 14 G Ground returns for low-side MOSFETs
SW1 20, 21 P Switching output of the regulator. Internally connected to both power MOSFETs. Connect to the power inductor.
SW2 28, 29 P
UDIM1 15 I Undervoltage lockout and external PWM dimming input. Connect to VIN through a resistor divider to implement input undervoltage protection. Diode couple external PWM signal to enable dimming. Locally decouple to GND using a 1-nF ceramic capacitor. Do not float.
UDIM2 2 I
V5A 8 P Analog supply voltage. Locally decouple to GND using a 100-nF to 1-µF ceramic capacitor located close to the controller.
V5D 9 P Digital supply voltage. Locally decouple to GND using a 2.2-µF to 4.7-µF ceramic capacitor located close to the controller.
VIN1 11, 12 P Power inputs and connections to high-side MOSFET drain node. Connect to the power supply and bypass capacitors CIN. The path from the VIN pin to high frequency bypass CIN and PGND must be as short as possible.
VIN2 5, 6 P