SLUSEG1A August   2021  – December 2021 TPS92519-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Buck Converter Switching Operation
      2. 7.3.2  Switching Frequency and Adaptive On-Time Control
      3. 7.3.3  Minimum On-Time, Off-Time, and Inductor Ripple
      4. 7.3.4  Enable
      5. 7.3.5  LED Current Regulation and Error Amplifier
      6. 7.3.6  Start-up Sequence
      7. 7.3.7  Analog Dimming and Forced Continuous Conduction Mode
      8. 7.3.8  External PWM Dimming and Input Undervoltage Lockout (UVLO)
      9. 7.3.9  Shunt FET Dimming or Matrix Beam Application
      10. 7.3.10 Bias Supply
      11. 7.3.11 Bootstrap Supply
      12. 7.3.12 Faults and Diagnostics
      13. 7.3.13 Output Short Circuit Fault
      14. 7.3.14 Output Open Circuit Fault
      15. 7.3.15 Parallel Operation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power On Reset (POR)
      2. 7.4.2 Run Mode
      3. 7.4.3 Sleep Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Duty Cycle Consideration
      2. 8.1.2  Switching Frequency Selection
      3. 8.1.3  LED Current Set Point
      4. 8.1.4  Inductor Selection
      5. 8.1.5  Output Capacitor Selection
      6. 8.1.6  Input Capacitor Selection
      7. 8.1.7  Bootstrap Capacitor Selection
      8. 8.1.8  Compensation Capacitor Selection
      9. 8.1.9  Input Undervoltage Protection
      10. 8.1.10 CSN Protection Diode
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Calculating Duty Cycle
        2. 8.2.2.2 Calculating Minimum On-Time and Off-Time
        3. 8.2.2.3 Minimum Switching Frequency
        4. 8.2.2.4 LED Current Set Point
        5. 8.2.2.5 Inductor Selection
        6. 8.2.2.6 Output Capacitor Selection
        7. 8.2.2.7 Bootstrap Capacitor Selection
        8. 8.2.2.8 Compensation Capacitor Selection
        9. 8.2.2.9 PWM Dimming and Input Voltage Protection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Compact Layout for EMI Reduction
        1. 10.1.1.1 Ground Plane
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.4 Thermal Information

THERMAL METRIC(1) DEVICE UNIT
DAP (HTSSOP)
32
RθJA Junction-to-ambient thermal resistance(2)(3) 26.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 16.3 °C/W
RθJB Junction-to-board thermal resistance 8.3 °C/W
ΨJT Junction-to-top characterization parameter 0.2 °C/W
ΨJB Junction-to-board characterization parameter 8.2 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 1.8 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
(2) The package thermal impedance is calculated in accordance with JESD51-7 standard with a 4-layer board and 2 W power dissipation.
(3) A heatsink or airflow would yield a much better RθJA.