SLUSEG1A August   2021  – December 2021 TPS92519-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Buck Converter Switching Operation
      2. 7.3.2  Switching Frequency and Adaptive On-Time Control
      3. 7.3.3  Minimum On-Time, Off-Time, and Inductor Ripple
      4. 7.3.4  Enable
      5. 7.3.5  LED Current Regulation and Error Amplifier
      6. 7.3.6  Start-up Sequence
      7. 7.3.7  Analog Dimming and Forced Continuous Conduction Mode
      8. 7.3.8  External PWM Dimming and Input Undervoltage Lockout (UVLO)
      9. 7.3.9  Shunt FET Dimming or Matrix Beam Application
      10. 7.3.10 Bias Supply
      11. 7.3.11 Bootstrap Supply
      12. 7.3.12 Faults and Diagnostics
      13. 7.3.13 Output Short Circuit Fault
      14. 7.3.14 Output Open Circuit Fault
      15. 7.3.15 Parallel Operation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power On Reset (POR)
      2. 7.4.2 Run Mode
      3. 7.4.3 Sleep Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Duty Cycle Consideration
      2. 8.1.2  Switching Frequency Selection
      3. 8.1.3  LED Current Set Point
      4. 8.1.4  Inductor Selection
      5. 8.1.5  Output Capacitor Selection
      6. 8.1.6  Input Capacitor Selection
      7. 8.1.7  Bootstrap Capacitor Selection
      8. 8.1.8  Compensation Capacitor Selection
      9. 8.1.9  Input Undervoltage Protection
      10. 8.1.10 CSN Protection Diode
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Calculating Duty Cycle
        2. 8.2.2.2 Calculating Minimum On-Time and Off-Time
        3. 8.2.2.3 Minimum Switching Frequency
        4. 8.2.2.4 LED Current Set Point
        5. 8.2.2.5 Inductor Selection
        6. 8.2.2.6 Output Capacitor Selection
        7. 8.2.2.7 Bootstrap Capacitor Selection
        8. 8.2.2.8 Compensation Capacitor Selection
        9. 8.2.2.9 PWM Dimming and Input Voltage Protection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Compact Layout for EMI Reduction
        1. 10.1.1.1 Ground Plane
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

-40°C ≤ TJ ≤ 150°C, V5D = V5A = 5 V, VIN = 24 V, VUDIMx = 5 V, CV5D =CV5A = 4.7 µF CBSTx = 0.1 µF, CCOMPx = 1 nF, RCSx = 100 mΩ, no load on SWx, FLTx pin floating (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
EXTERNAL ANALOG AND GATE DRIVE SUPPLIES (V5D, V5A)
VV5D,A(UVLO) V5D and V5A UVLO threshold Rising 4.10 4.26 V
Falling 3.84 4.00 V
Hysteresis 100 mV
IV5A(STBY) Analog supply stand-by current VUDIM1 = VUDIM2 = 0 V 4 5.5 mA
IV5D(STBY) Gate drive supply stand-by current VUDIM1 = VUDIM2 = 0 V 0.9 1.3 mA
IV5A(SLEEP) Analog supply sleep state current VEN = 0 V 14 300 nA
IV5D(SLEEP) Gate drive supply sleep state current VEN = 0 V 17 24 µA
IVINx(SLEEP) VIN pin sleep state current VINx = 15 V, VEN = 0 V 2 4 μA
IV5D(SW) Gate drive supply switching current VV5D = 5 V, VFSET = 5 V,  CH1 and CH2 switching 6 10 mA
ENABLE INPUT (EN)
VEN Enable voltage rising threshold 1.8 V
Enable voltgae falling threshold 0.8 mV
IEN Enable input bias current 10 µA
HIGH-SIDE FET (SWx, BOOTx)
RDSx(ON-HS) High-side MOSFET on resistance VINx = 6 V, VBSTx = 11 V, IHSx = 100 mA 240 465 mΩ
VBSTx(UV) Bootstrap UVLO threshold Falling, VINx = 6 V, VSWx = 0 V 2.60 2.95 3.30 V
Hysteresis, VINx = 6 V, VSWx = 0 V 115 184 245 mV
IQ(xBST) Bootstrap pin quiescent current VBSTx = 5 V, VSWx = 0 V 200 250 300 µA
LOW-SIDE FET (SWx)
RDSx(ON-LS) Low-side MOSFET on resistance VINx = 6 V, ILSx = 100 mA 240 465 mΩ
HIGH-SIDE FET CURRENT LIMIT
IHSx(ILIM) High-side current limit threshold VINx = 6 V 2.8 3.5 4.2 A
tHSx(LEB) High-side current sense leading-edge blanking period VINx = 6 V 35 60 80 ns
tHSx(RES) Current limit response time VINx = 6 V 20 ns
LOW-SIDE FET CURRENT LIMIT
ILSx(ILIM) Low-side sinking current limit threshold VINx = 6 V 1.67 2.50 3.5 A
tLSx(LEB) Low-side current sense leading-edge blanking period VINx = 6 V 76 ns
SWITCHING FREQUENCY (FSET)
VFSET Frequency set input rising threshold 1.8 V
Frequency set input falling threshold 0.8 V
IFSET Frequency set input bias current 10 µA
tON(SW1) Channel 1 on-time VFSET = 0 V, VIN = 50 V, VCSP = 38 V 384 ns
VFSET = 5 V, VIN = 50 V, VCSP = 25 V 1.36 µs
tON(SW2) Channel 2 on-time VFSET = 0 V, VIN = 50 V, VCSP = 38 V 365 ns
VFSET = 5 V, VIN = 50 V, VCSP = 25 V 1.20 µs
ANALOG ADJUST SETTING AND CURRENT SENSE AMPLIFIER (IADJx, CSPx, CSNx)
VIADJx(CLP) IADJx internal limit 2.38 2.45 2.52 V
VIADJx(SD) Shutdown threshold Rising, VINx = 6 V 140 mV
Falling, VINx = 6 V 100 mV
V(CSPx-CSNx) Current sense threshold VCSPx = 6 V,
VIADJx > 2.45V		 167.5 173.0 178.5 mV
VCSPx = 6 V,
VIADJx = 1.22V		 83.0 88.5 94.0 mV
VCSPx = 6 V,
VIADJx = 460mV		 29.0 34.5 40.0 mV
VCSPx = 6 V,
VIADJx = 150mV		 6.5 12.5 18.5 mV
gmx(LV) Level shift amplifier transconductance VINx = 63 V, VCSNx = 5 V 50 µA/V
VCSPx(SHT) Output short circuit detection threshold Rising 1.71 V
Falling 1.50 V
ON-TIME GENERATOR
tONx(MIN) Minimum on-time. VINx = 4.5 V 90 110 130 ns
OFF-TIME GENERATOR
tOFFx(MIN) Minimum off-time VINx = 4.5 V 57 78 86 ns
PWM DIMMING and PROGRAMMABLE UVLO INPUT (DIMx)
VUDIMx(DO) UDIM dropout detection threshold Rising 2.45 2.52 V
Falling 1.95 2.35 V
VUDIMx(EN) UDIM undervoltage lockout threshold Rising 1.22 1.27 V
Falling 0.97 1.02 V
IUDIMx(UVLO) UDIM source current (UVLO hysteresis) VUDIMx = 1.5 V 6.3 10 12 µA
ERROR AMPLIFIER (COMPx)
gM Transconductance VINx = 63 V 450 µA/V
ICOMPx(SRC) COMPx current source capacity VINx = 63 V, V(CSPx–CSNx) = 0 V, VIADJx = 1.4 V 45 µA
ICOMPx(SINK) COMPx current sink capacity VINx = 63 V, V(CSPx–CSNx) = 200 mV, VIADJx = 1.4 V 45 µA
EAx(BW) Bandwidth Unity gain 3 MHz
EA(VD) Input differential sense range –225 225 mV
EA(CM) Input common mode range VINx = 63 V 0 VINx – 0.5 V
ICOMPx(LKG) COMPx leakage current VUDIMx = 0 V 2.5 nA
VCOMPx(ST) COMPx startup threshold Rising 2.45 V
Hysteresis 425 mV
VCOMPx(OV) COMPx over-voltage detection threshold Rising 3.0 3.2 V
Hysteresis 75 mV
RCOMPx(DCH) COMPx discharge FET resistance 230 Ω
VCOMPx(RST) Reset voltage Falling 100 mV
FAULT INDICATOR (FLT)
R(FLTx) Fault pin pull-down resistance 3 7 Ω
TOC Hiccup retry delay time 3.6 ms
THERMAL SHUTDOWN
TSD Thermal shutdown threshold 175 °C