SLUSD66D September 2019 – February 2021 TPS92520-Q1
PRODUCTION DATA
The SPI-accessible registers are each eight bits wide and exist in a six-bit addressable register array (0x00 through 0x3F). The registers in the TPS92520-Q1 device contain programmed information and operating status. Upon power up, the registers are reset to the default values. Writes to unlisted addresses are not permitted and can result in undesired operation. Reads of unlisted addresses return the zero value.
Reserved bits ("RESERVED") must be written with '0' values when writing. Registers are read or write unless indicated otherwise in the description of the register. Table 7-4 lists the TPS92520-Q1 register map.
ADDR | REGISTER | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | DEFAULT | ||
---|---|---|---|---|---|---|---|---|---|---|---|---|
0x00 | SYSCFG1 | FPINRST | PWMPH | LHSW | CMWEN | CH2INTPWM | CH2EN | CH1INTPWM | CH1EN | 00010000 | ||
0x01 | SYSCFG2 | IFT[1:0] | CH2TSFL | CH2HSILIMFL | CH2LSILIMFL | CH1TSFL | CH1HSILIMFL | CH1LSILIMFL | 00000000 | |||
0x02 | CMWTAP | RESERVED | CMWTAP[3:0] | 00001000 | ||||||||
0x03 | STATUS1 | CH2LSILIM | CH2HSILIM | CH2SHORT | CH2COMPOV | CH1LSILIM | CH1HSILIM | CH1SHORT | CH1COMPOV | n/a | ||
0x04 | STATUS2 | RESERVED | CH2TP | CH2BSTUV | CH2TOFFMIN | CH1TP | CH1BSTUV | CH1TOFFMIN | n/a | |||
0x05 | STATUS3 | STANDALONE | V5AUV | CMWTO[1:0] | TW | PC | CH2STATUS | CH1STATUS | n/a | |||
0x06 | TWLMT | TWLMT[9:2] | 10001010 | |||||||||
0x07 | SLEEP | RESERVED | SLEEP[1:0] | 00000000 | ||||||||
0x08 | CH1IADJL | RESERVED | CH1IADJ[1:0] | 00000000 | ||||||||
0x09 | CH1IADJH | CH1IADJ[9:2] | 00000000 | |||||||||
0x0A | CH2IADJL | RESERVED | CH2IADJ[1:0] | 00000000 | ||||||||
0x0B | CH2IADJH | CH2IADJ[9:2] | 00000000 | |||||||||
0x0C | PWMDIV | RESERVED | PWMDIV[2:0] | 00000100 | ||||||||
0x0D | CH1PWML | CH1PWM[7:0] | 00000000 | |||||||||
0x0E | CH1PWMH | RESERVED | CH1PWM[9:8] | 00000000 | ||||||||
0x0F | CH2PWML | CH2PWM[7:0] | 00000000 | |||||||||
0x10 | CH2PWMH | RESERVED | CH2PWM[9:8] | 00000000 | ||||||||
0x11 | CH1TON | RESERVED | CH1TON[5:0] | 00000111 | ||||||||
0x12 | CH2TON | RESERVED | CH2TON[5:0] | 00000111 | ||||||||
0x13 | CH1VIN | CH1VIN[7:0] | n/a | |||||||||
0x14 | CH1VLED | CH1VLED[7:0] | n/a | |||||||||
0x15 | CH1VLEDON | CH1VLEDON[7:0] | n/a | |||||||||
0x16 | CH1VLEDOFF | CH1VLEDOFF[7:0] | n/a | |||||||||
0x17 | CH2VIN | CH2VIN[7:0] | n/a | |||||||||
0x18 | CH2VLED | CH2VLED[7:0] | n/a | |||||||||
0x19 | CH2VLEDON | CH2VLEDON[7:0] | n/a | |||||||||
0x1A | CH2VLEDOFF | CH2VLEDOFF[7:0] | n/a | |||||||||
0x1B | TEMPL | RESERVED | TEMP[1:0] | n/a | ||||||||
0x1C | TEMPH | TEMP[9:2] | n/a | |||||||||
0x1D | V5D | V5D[7:0] | n/a | |||||||||
0x1E | LHCFG1 | LHPWMPH | LHEXTIADJ | LH2100DC | LH2INTPWM | LH2EN | LH1100DC | LH1INTPWM | LH1EN | 00000000 | ||
0x1F | LHCFG2 | LHIFT[1:0] | LH2TSFL | LH2HSILIMFL | LH2LSILIMFL | LH1TSFL | LH1HSILIMFL | LH1LSILIMFL | 00000000 | |||
0x20 | LHIL | RESERVED | LHI[1:0] | n/a | ||||||||
0x21 | LHIH | LHI[9:2] | n/a | |||||||||
0x22 | LHIFILTL | LHIFILT[1:0] | n/a | |||||||||
0x23 | LHIFILTH | LHIFILT[9:2] | ||||||||||
0x24 | LH1IADJL | RESERVED | LH1IADJ[1:0] | 00000000 | ||||||||
0x25 | LH1IADJH | LH1IADJ[9:2] | 00000000 | |||||||||
0x26 | LH2IADJL | RESERVED | LH2IADJ[1:0] | 00000000 | ||||||||
0x27 | LH2IADJH | LH2IADJ[9:2] | 00000000 | |||||||||
0x28 | LHCH1PWML | LH1PWM[7:0] | 00000000 | |||||||||
0x29 | LHCH1PWMH | RESERVED | LH1PWM[9:8] | 00000000 | ||||||||
0x2A | LHCH2PWML | LH2PWM[7:0] | 00000000 | |||||||||
0x2B | LHCH2PWMH | RESERVED | LH2PWM[9:8] | 00000000 | ||||||||
0x2C | LH1TON | RESERVED | LH1TON[5:0] | 00000111 | ||||||||
0x2D | LH2TON | RESERVED | LH2TON[5:0] | 00000111 | ||||||||
0x2E | RESET | RESET[7:0] | 00000000 |
Complex bit access types are encoded to fit into small table cells. Table 7-5 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
W | W | Write |
R | R | Read |
R/W | R/W | Read and Write |
RC | RC | Read to clear |
-n | Value after reset or the default value |
The following sections provide the descriptions for different registers.