SLUSBP5E March   2014  – July 2018 TPS92601-Q1 , TPS92602-Q1

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1. 3.1 Typical Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Fixed-Frequency PWM Control
      2. 7.3.2 Slope-Compensation Output Current
      3. 7.3.3 Boost-Current Limit
      4. 7.3.4 Oscillator and PLL
      5. 7.3.5 Control Loop Compensation
      6. 7.3.6 LED Open-Circuit Detection
      7. 7.3.7 Output Short-Circuit and Overcurrent Detection
      8. 7.3.8 Measuring LED Current During a Non-Failure Condition
      9. 7.3.9 LED Dimming Options
        1. 7.3.9.1 Analog Dimming
        2. 7.3.9.2 PWM Dimming
    4. 7.4 Device Functional Modes
      1. 7.4.1 Undervoltage and Overvoltage Shutdown
      2. 7.4.2 Overtemperature Shutdown
      3. 7.4.3 Device State Diagram
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Boost Regulator With Separate or Paralleled Channels
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1  Switching Frequency
          2. 8.2.1.2.2  Maximum Output-Current Set Point
          3. 8.2.1.2.3  Output Overvoltage-Protection Set Point
          4. 8.2.1.2.4  Duty Cycle Estimation
          5. 8.2.1.2.5  Inductor Selection
          6. 8.2.1.2.6  Rectifier Diode Selection
          7. 8.2.1.2.7  Output Capacitor Selection
          8. 8.2.1.2.8  Input Capacitor Selection
          9. 8.2.1.2.9  Current Sense and Current Limit
          10. 8.2.1.2.10 Switching MOSFET Selection
          11. 8.2.1.2.11 Loop Compensation
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Boost-to-Battery Regulator
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1  Switching Frequency
          2. 8.2.2.2.2  Maximum Output-Current Set Point
          3. 8.2.2.2.3  Output Overvoltage-Protection Set Point
          4. 8.2.2.2.4  Duty Cycle Estimation
          5. 8.2.2.2.5  Inductor Selection
          6. 8.2.2.2.6  Rectifier Diode Selection
          7. 8.2.2.2.7  Output Capacitor Selection
          8. 8.2.2.2.8  Input Capacitor Selection
          9. 8.2.2.2.9  Current Sense and Current Limit
          10. 8.2.2.2.10 Switching MOSFET Selection
          11. 8.2.2.2.11 Loop Compensation
        3. 8.2.2.3 TPS92602y-Q1 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Related Links
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.5 Control Loop Compensation

Modeling of the TPS9260xy-Q1 control loop is like that for any current-mode controller. Using a first-order approximation, one can model the uncompensated loop as a single pole created by the output capacitor and, in the boost and buck-boost topologies, a right half-plane zero created by the inductor, where both have a dependence on the dynamic resistance of the LED string. There is also in the model a high-frequency pole which, however, is near the switching frequency and plays no part in the compensation design process. Therefore, the loop analysis neglects this high-frequency pole. Because TI recommends ceramic capacitors for use with LED drivers due to long lifetimes and high ripple-current rating, one can also neglect the ESR of the output capacitor in the loop analysis. Finally, there is a dc gain of the uncompensated loop which depends on internal controller gains and the external sensing network. A boost regulator serves as an example case. See the Detailed Design Procedure section for compensation of all topologies.

Equation 3 gives the whole-loop gain for a boost regulator.

Equation 3. TPS92601-Q1 TPS92602-Q1 eq04_Tu_slusbp5.gif

Equation 4 approximates the output pole (ωep0).

Equation 4. TPS92601-Q1 TPS92602-Q1 eq05_wepo_slusbp5.gif

where

  • r(D): LED and R(ILED_SNS) dynamic resistance
  • CO: Output capacitor

Use Equation 5 to calculate the right half-plane zero (ωezrhp).

Equation 5. TPS92601-Q1 TPS92602-Q1 eq06_wezrhp_slusbp5.gif

Use Equation 6 to calculate the output capacitor and ESR zero (ωezc).

Equation 6. TPS92601-Q1 TPS92602-Q1 eq07_wezc_slusbp5.gif

The EA transfer function with compensation capacitor and resistor of the system is described in Equation 7 is shown in Equation 7.

Equation 7. TPS92601-Q1 TPS92602-Q1 eq08_Tuo_slusbp5.gif

where

    Use Equation 8 to calculate the EA output with compensation capacitor pole (ωep1).

    Equation 8. TPS92601-Q1 TPS92602-Q1 eq09_wep1_slusbp5.gif

    where

      The EA higher frequency pole (ωep2 to filter the high-frequency noise, which is higher than whole-loop bandwidth) is shown in Equation 9.

      Equation 9. TPS92601-Q1 TPS92602-Q1 eq10_wep2_slusbp5.gif

      The EA output ESR zero (ωez1) is shown in Equation 10.

      Equation 10. TPS92601-Q1 TPS92602-Q1 eq11_wez1_slusbp5.gif

      Compensator design should give adequate phase margin (above 45°) at the crossover frequency. A simple compensator using a single capacitor at the COMP pin adds a dominant pole to the system, which ensures adequate phase margin if placed low enough. At high duty cycles, the RHP zero places extreme limits on the achievable bandwidth with this type of compensation. However, because an LED driver is essentially free of output transients (except catastrophic failures, open or short), the dominant pole approach, even with reduced bandwidth, is usually the best approach.