SLUSBP5E March   2014  – July 2018 TPS92601-Q1 , TPS92602-Q1

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1. 3.1 Typical Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Fixed-Frequency PWM Control
      2. 7.3.2 Slope-Compensation Output Current
      3. 7.3.3 Boost-Current Limit
      4. 7.3.4 Oscillator and PLL
      5. 7.3.5 Control Loop Compensation
      6. 7.3.6 LED Open-Circuit Detection
      7. 7.3.7 Output Short-Circuit and Overcurrent Detection
      8. 7.3.8 Measuring LED Current During a Non-Failure Condition
      9. 7.3.9 LED Dimming Options
        1. 7.3.9.1 Analog Dimming
        2. 7.3.9.2 PWM Dimming
    4. 7.4 Device Functional Modes
      1. 7.4.1 Undervoltage and Overvoltage Shutdown
      2. 7.4.2 Overtemperature Shutdown
      3. 7.4.3 Device State Diagram
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Boost Regulator With Separate or Paralleled Channels
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1  Switching Frequency
          2. 8.2.1.2.2  Maximum Output-Current Set Point
          3. 8.2.1.2.3  Output Overvoltage-Protection Set Point
          4. 8.2.1.2.4  Duty Cycle Estimation
          5. 8.2.1.2.5  Inductor Selection
          6. 8.2.1.2.6  Rectifier Diode Selection
          7. 8.2.1.2.7  Output Capacitor Selection
          8. 8.2.1.2.8  Input Capacitor Selection
          9. 8.2.1.2.9  Current Sense and Current Limit
          10. 8.2.1.2.10 Switching MOSFET Selection
          11. 8.2.1.2.11 Loop Compensation
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Boost-to-Battery Regulator
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1  Switching Frequency
          2. 8.2.2.2.2  Maximum Output-Current Set Point
          3. 8.2.2.2.3  Output Overvoltage-Protection Set Point
          4. 8.2.2.2.4  Duty Cycle Estimation
          5. 8.2.2.2.5  Inductor Selection
          6. 8.2.2.2.6  Rectifier Diode Selection
          7. 8.2.2.2.7  Output Capacitor Selection
          8. 8.2.2.2.8  Input Capacitor Selection
          9. 8.2.2.2.9  Current Sense and Current Limit
          10. 8.2.2.2.10 Switching MOSFET Selection
          11. 8.2.2.2.11 Loop Compensation
        3. 8.2.2.3 TPS92602y-Q1 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Related Links
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.2.2.11 Loop Compensation

The COMP pin on the TPS92602y-Q1 device is for external compensation, allowing optimization of the loop response for each application. The COMP pin is the output of the internal transconductance amplifier. The external resistor R7, along with ceramic capacitors C5 and C6 (see Figure 22 ), connect to the COMP pin to provide poles and zero. The poles and zero, along with the inherent pole and zero in a peak-current-mode control boost converter, determine the closed-loop frequency response. This is important to converter stability and transient response. The first step is to calculate the pole and the right half-plane zero of the peak-current-mode boost converter by Equation 73 and Equation 74. To make the loop stable, the loop must have sufficient phase margin at the crossover frequency where the loop gain is 1. To avoid the effect of the right half-plane zero on the loop stability, choose the crossover frequency less than 1/5 of f(ZRHP).

Equation 73. TPS92601-Q1 TPS92602-Q1 eq36_fp_SLUSBP5.gif

where

  • C(OUT) is the bulk output capacitance previously calculated
  • R(OUT) is the effective output impedance
Equation 74. TPS92601-Q1 TPS92602-Q1 eq37_fZRHP_SLUSBP5.gif
Equation 75. TPS92601-Q1 TPS92602-Q1 eq38_Rout_SLUSBP5.gif

where

    The loop compensation consists of a series resistor and capacitor (R(COMP) and C(COMP)) from COMP to SGND. R(COMP) sets the crossover frequency and C(COMP) sets the zero frequency of the integrator. For optimum performance, use the following equations:

    Equation 76. gM(COMP) = 1000
    Equation 77. TPS92601-Q1 TPS92602-Q1 eq39_Rcomp_SLUSBP5.gif
    Equation 78. TPS92601-Q1 TPS92602-Q1 eq40_Ccomp_SLUSBP5.gif

    where

      An output capacitor that is an electrolytic capacitor which has large ESR requires a capacitor to cancel the zero of the output capacitor. Equation 79 calculates the value of this capacitor.

      Equation 79. TPS92601-Q1 TPS92602-Q1 eq41_C6_SLUSBP5.gif