SLVSCK5C September   2014  – January 2020 TPS92638-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Typical Application Schematic
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 LED Current Setting
      2. 9.3.2 PWM Control
      3. 9.3.3 Fault Diagnostics
        1. 9.3.3.1 Open-Load Detection
      4. 9.3.4 Thermal Foldback
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 PWM Dimming by Bank
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Performance Plots
      2. 10.2.2 Two Brightness Levels for TAIL and STOP Lights
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
      3. 10.2.3 PWM Dimming by Modulated Supply
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Design Procedure
      4. 10.2.4 Driving LEDs From a Single Device With Channels in Parallel
        1. 10.2.4.1 Design Requirements
        2. 10.2.4.2 Design Procedure
      5. 10.2.5 Driving LEDs From Multiple Devices With Channels in Parallel
        1. 10.2.5.1 Design Requirements
        2. 10.2.5.2 Design Procedure
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 Thermal Information
  13. 13Device and Documentation Support
    1. 13.1 Trademarks
    2. 13.2 Electrostatic Discharge Caution
    3. 13.3 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics

V(VIN) = 14 V, TJ = –40°C to 150°C (unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE AND CURRENT (SUPPLY)
I(Quiescent) Quiescent current V(PWMx), V(EN) = high, I(IOUTx) = 40 mA 0.5 0.6 0.9 mA
I(Shutdown) Shutdown current V(PWMx) = 0 V, V(EN) = 0 V 10 µA
I(fault) Shutdown current in fault mode (device to GND) V(PWMx), V(EN) = high, V(FAULT) = low,
V(SUPPLY) = 5 V to 40 V, I(IOUTx) = 30 mA		 0.5 0.75 1 mA
Shutdown current in fault mode (from SUPPLY) 1.15
PWM, EN, STOP
I(EN-pd) EN internal pulldown V(EN) = 0 V to 40 V 0.5 5 µA
VIH(PWMx) Logic input, high level(1) PWMx rising from a low state, IOUTx disabled 1.161 1.222 1.283 V
VIL(PWMx) Logic input, low level(1) PWMx falling from a high state, IOUTx enabled 1.119 1.178 1.237 V
V(PWM-hys) Hysteresis 44 mV
I(PWM-pd) PWMx internal pulldown current V(PWMx) = 0 V to 20 V 180 300 nA
V(PWMx) = 20 V to 40 V 0.2 2 µA
I(STOP-PD) STOP internal pulldown V(STOP) = 0 V to 40 V 0.1 1 µA
 CURRENT REGULATION (IOUTx)
I(IOUTx) Regulated output current range Each channel, V(PWMx) = high, V(EN) = high V(SUPPLY) > 5 V, V(IOUTx) > 0.9 V 2 70 mA
I(IOUT_TOTAL) 8 channels in parallel mode, V(PWMx) = high, V(EN) = high, V(SUPPLY) > 5 V, V(IOUTx) > 0.9 V 16 560 mA
ΔIO(channel) Channel accuracy 5 mA ≤ I(IOUTx) < 10 mA, V(SUPPLY) = 5 V–40 V
Channel accuracy = (I(IOUTx) – I(avg)) / I(avg)(2) 		–7% 7%
10 mA ≤ I(IOUTx) ≤ 70 mA, V(SUPPLY) = 5 V–40 V
Channel accuracy = (I(IOUTx) – I(avg)) / I(avg)(2) 		–3% 3%
2 mA ≤ I(IOUTx) < 5 mA, V(SUPPLY) = 5 V–40 V
Channel accuracy = (I(IOUTx) – I(avg)) / I(avg)(2) 		–18% 18%
ΔIO(device) Device accuracy 5 mA ≤ I(IOUTx) < 10 mA, V(SUPPLY) = 5 V to 20 V
Device accuracy = (I(IOUTx) – I(setting)) / I(setting)(3) 		–8% 8%
10 mA ≤ I(IOUTx) ≤ 70 mA, V(SUPPLY) = 5 V to 20 V
Device accuracy = (I(IOUTx) – I(setting)) / I(setting)(3) 		–4% 4%
2 mA ≤ I(IOUTx) < 5 mA, V(SUPPLY) = 5 V to 20 V
Device accuracy = (I(IOUTx) – I(setting)) / I(setting)(3) 		–20% 20%
5 mA ≤ I(IOUTx) < 10 mA, V(SUPPLY) = 20 V to 40 V
Device accuracy = (I(IOUTx) – I(setting)) / I(setting)(3) 		–10% 10%
10 mA ≤ I(IOUTx) ≤ 70 mA, V(SUPPLY) = 20 V to 40 V
Device accuracy = (I(IOUTx) – I(setting)) / I(setting)(3) 		–8% 8%
2 mA ≤ I(IOUTx) < 5 mA, V(SUPPLY) = 20 V to 40 V
Device accuracy = (I(IOUTx) – I(setting)) / I(setting)(3) 		–20% 20%
V(REF) Reference voltage I(IOUTx) = 20 mA 1.198 1.222 1.246 V
V(REFHI) STOP reference voltage 1.198 1.222 1.246 V
G(I) Ratio of I(IOUTx) to reference current
I(IOUTx) / I(REF) or I(IOUTx) / ( I(REF) + I(REFHI))		 200 mA/mA
V(DROP_IOUTx) Dropout voltage I(IOUTx) = 70 mA 0.71 0.9 V
V(DROP) I(IOUTx) = 35 mA 0.28 0.45 V
I(slew) Current slew-rate rise and fall times Current rising from 10% to 90% or falling from 90% to 10% at I(IOUTx) = 35 mA.(4) 1.5 6 12 mA/µs
Current rising from 10% to 90% or falling from 90% to 10% at I(IOUTx) = 70 mA.(4) 3 6 12 mA/µs
FAULT (FAULT)
VOL Logic output low level 500-µA external pullup 0.4 V
VOH Logic output high level 1-µA external pulldown 2 V
I(pulldown) Strong pulldown current 600 780 1000 µA
I(pullup) Pullup current 4 8 12 µA
PROTECTION
V(OL_th) Open-load detection voltage
V(OL_TH) = V(SUPPLY) – V(IOUTx) 		50 100 150 mV
V(OL_hys) Open-load detection hysteresis 100 200 300 mV
V(SHORT_th) Short-detection voltage 0.846 0.89 0.935 V
V(SHORT_hys) Short-detection hysteresis 318 335 352 mV
N(SHORT_deg) Open-load detection PWM deglitch cycle number 7 8 Cycles
R(REF_th),
R(REFHI_th) 		REF and REFHI pins, parallel-resistor short detection 1400 2300 Ω
THERMAL MONITOR
T(shutdown) Thermal shutdown 155 170 °C
T(hys) Thermal shutdown hysteresis 15 °C
T(th) Thermal foldback activation temperature I(IOUTx) = 90% × I(setting), TEMP terminal floating 95 110 125 °C
I(TFC-min) Minimum foldback current, ratio of I(setting) 40% 50% 60%
V(T-disable) Thermal-foldback-function disable threshold of V(TEMP) 0 0.2 V
K(temp1) Change of V(TEMP) relative to T(J) 25 mV/°C
(1) VIH and VIL track each other. That is, both are simultaneously at MAX, MIN, or the same intermediate point. Therefore, there can be no overlap of the VIH and VIL values during normal operation.
(2) I(AVG) = [I(IOUT1) + I(IOUT2) + I(IOUT3) + I(IOUT4) + I(IOUT5) + I(IOUT6) + I(IOUT7) + I(IOUT8)] / 8
(3) I(setting) is the target current set by R(REF).
(4) See Parameter Measurement Information for the load model for the slew-rate test and delay-time test.