SLUSCV5 May 2022 TPS92643-Q1
PRODUCTION DATA
The following operating description of the TPS92643-Q1 refers to the Functional Block Diagram and the waveforms in Figure 7-1. The main control loop of the TPS92643-Q1 is based on an adaptive on-time pulse width modulation (PWM) technique that combines a constant on-time control with an inductor valley current sense circuit for pseudo-fixed frequency operation. This proprietary control technique enables closed-loop regulation of LED current and fast dynamic response necessary to meet the requirements for dimming animation and fault protection.
In steady state, the high-side MOSFET is turned on at the beginning of each cycle. The on-time duration of this MOSFET is controlled by an internal one-shot timer and the high-side MOSFET is turned off after the timer expires. The one-shot timer duration is set by the output voltage measured at the CSP pin, VCSP, and the input voltage measured at the VIN pin, VIN, to maintain a pseudo-fixed frequency. During the on-time interval, the inductor current increases with a slope proportional to the voltage applied across its terminals (VIN – VCSP).
The low-side MOSFET is turned on after a fixed dead time and the inductor current then decreases with the constant slope proportional to the output voltage, VCSP. Inductor current measured by the external sense resistor is compared to the valley threshold, VVAL, by an internal high-speed comparator. This MOSFET is turned off and the one-shot timer is initiated when the sensed inductor current falls below the valley threshold voltage. The high-side MOSFET is turned on again after a fixed dead time.
The internal rail-to-rail error amplifier sets the valley threshold voltage and regulates the average inductor current based on a reference value set by VIADJ pin. A simple integral loop compensation circuit consisting of a capacitor connected from the COMP pin to GND provides a stable and high-bandwidth response. As the inductor current is directly sensed by an external resistor, the device operation is not sensitive to the ESR of the output capacitors and is compatible with common multilayered ceramic capacitors (MLCC).