The TPS92682-Q1 is a dual-channel, peak current-mode controller with SPI communication interface. The device is programmable to operate in constant-voltage (CV) or constant-current (CC) modes.
In CV mode, TPS92682-Q1 can be programmed to operate as two independent or dual-phase Boost voltage regulators. The output voltage can be programmed using an external resistor voltage divider, and a SPI-programmable 8-bit DAC.
In CC mode, the device is designed to support dual channel step-up or step-down LED driver topologies. LED current can be independently modulated using analog or PWM dimming techniques. Analog dimming with over 28:1 range is obtained using a programmable 8-bit DAC. PWM dimming of LED current is achieved either by directly modulating the PWM input pins with the desired duty cycle, or using a SPI-programmable 10-bit PWM counter. The optional PDRV gate driver output can be used to drive an external P-Channel series MOSFET.
The TPS92682-Q1 incorporates an advanced SPI-programmable diagnostic and fault protection mechanism including: cycle-by-cycle current limit, output overvoltage and undervoltage protection, ILED overcurrent protection, and thermal warning. The device also includes an open-drain fault indicator output per channel.
The TPS92682-Q1 includes an LH pin, when pulled high, initiates the limp home (LH) condition. In LH mode, the device uses a separate set of SPI-programmed registers.
PART NUMBER | PACKAGE(1) | BODY SIZE (NOM) |
---|---|---|
TPS92682-Q1 | VQFN (32) | 5.0 mm x 5.0 mm |
TPS92682-Q1 | HTSSOP (32) | 11.0 mm x 6.1 mm |
Changes from Revision B (July 2020) to Revision C (March 2021)
Changes from Revision A (August 2019) to Revision B (July 2020)
Changes from Revision () to Revision ()
Changes from Revision * (March 2019) to Revision A (August 2019)
PIN | I/O(1) | DESCRIPTION | ||
---|---|---|---|---|
NAME | VQFN NO. | HTSSOP NO. | ||
AGND | 30 | 11 | P | Signal ground |
COMP1 | 29 | 10 | I/O | Connect to an integral or integral-proportional compensation network to ensure stability for channel-1. |
COMP2 | 12 | 25 | I/O | Connect to an integral or integral-proportional compensation network to ensure stability for channel-2. |
CSN1 | 27 | 8 | I | High-side current sense amplifier input (–) for channel-1 |
CSN2 | 14 | 27 | I | High-side current sense amplifier input (–) for channel-2 |
CSP1 | 26 | 7 | I | High-side current sense amplifier input (+) for channel-1 |
CSP2 | 15 | 28 | I | High-side current sense amplifier input (+) for channel-2 |
EN | 2 | 15 | I | Hardware enable. Pull this pin low to enter shutdown. |
FB1/OV1 | 25 | 6 | I/O | Connect using a resistor divider to VOUT1 to set OVP threshold (and VOUT in CV mode) for channel-1. |
FB2/OV2 | 16 | 29 | I/O | Connect using a resistor divider to VOUT2 to set OVP threshold (and VOUT in CV mode) for channel-2. |
FLT1 | 10 | 23 | O | Open-drain fault output for channel-1 (or both channels if PIN-11 is programmed to be SYNC). |
FLT2/SYNC | 11 | 24 | I/O | Dual function pin (programmable) either open-drain fault output for channel-2 or SYNC input |
GATE1 | 22 | 3 | I/O | Channel-1 gate driver output for external N-channel FET |
GATE2 | 19 | 32 | I/O | Channel-2 gate driver output for external N-channel FET |
ISN1 | 24 | 5 | I | Switch current sense input (-) for channel-1. Connect to the GND connection of the external switch-current sense resistor. |
ISN2 | 17 | 30 | I | Switch current sense input (-) for channel-2. Connect to the GND connection of the external switch-current sense resistor. |
ISP1 | 23 | 4 | I | Switch current sense input (+) for channel-1. Connect to external switch current sense resistor between N-channel FET and ground. |
ISP2 | 18 | 31 | I | Switch current sense input (+) for channel-2. Connect to external switch current sense resistor between N-channel FET and ground. |
LH | 9 | 22 | I | Digital input, when set high, the device enters the limp home mode. |
MISO | 7 | 20 | O | SPI slave data output |
MOSI | 8 | 21 | I | SPI slave data input |
PDRV1 | 28 | 9 | I/O | Channel-1 P-channel gate driver. Connect to gate of external series P-channel FET switch. |
PDRV2 | 13 | 26 | I/O | Channel-2 P-channel gate driver. Connect to gate of external series P-channel FET switch. |
PWM1 | 3 | 16 | I | Connect to external PWM signal to enable PWM dimming for channel-1. |
PWM2 | 4 | 17 | I | Connect to external PWM signal to enable PWM dimming for channel-2. |
PGND | 20 | 1 | P | Power ground |
RT | 32 | 13 | I/O | Set internal clock frequency by connecting a resistor to ground |
SCK | 6 | 19 | I | SPI clock input |
SSN | 5 | 18 | I | SPI chip select input |
VCC | 21 | 2 | P | 7.5-V low-dropout regulator output |
VDD | 31 | 12 | P | 5-V LDO output |
VIN | 1 | 14 | P | High-voltage input (65 V) to internal LDO |