SLUSCX8C March 2019 – March 2021 TPS92682-Q1
PRODUCTION DATA
Configuration register 1
ADDR | REGISTER | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | DEFAULT |
---|---|---|---|---|---|---|---|---|---|---|
01h | CFG1 | PWMPH | INTPWM | 2PH | LH | CH2HG | CH1HG | CH2CV | CH1CV | 00000000 |
0: Phase shift of 180° between internal PWM signals
1: Zero phase shift between internal PWM signals
0: External PWM inputs are used.
1: Internal PWM inputs are used.
0: Single phase, two-channel configuration
1: Dual phase configuration
This bit is latched high when the LH pin is set high. The LH bit remains high until this bit is written back to zero through SPI (the LH pin cannot set this bit to zero). If the LH bit is high, the LH registers are used to control the logic instead of the normal registers. The part comes out of LH mode when LH pin is pulled low and the LH bit is written to 0.
It is recommended that the LH bit always be written with a ‘1’ during normal programming. This will ensure that a true limp-home event triggered by LH pin is captured.
0: The error-amp of the associated channel is set to low gain.
1: The error-amp of the associated channel is set to high gain.
0: The associated channel is set in CC mode.
1: The associated channel is set in CV mode.