SLUSCX8 Data sheet

SLUSCX8C March 2019 – March 2021 TPS92682-Q1

PRODUCTION DATA

Package Options

Mechanical Data (Package|Pins)

DAP|32
- MPDS380A
RHB|32
- MPQF130D
RHM|32
- MPQF152B

Thermal pad, mechanical data (Package|Pins)

DAP|32
- PPTD363
RHB|32
- QFND644
RHM|32
- QFND588

Orderable Information

7.5.1 Serial Interface

The SPI bus consists of four signals: SSN, SCK, MOSI, and MISO. The SSN, SCK, and MOSI pins are TTL inputs into the TPS92682-Q1 while the MISO pin is an open-drain output. The SPI bus can be configured for both star-connect and daisy chain hardware connections.

A bus transaction is initiated by the MCU creating a falling edge on SSN. While SSN is low, the input data present on the MOSI pin is sampled on the rising edge of SCK, with MS-bit first. The output data is asserted on the MISO pin at the falling edge of the SCK. Figure 7-22 shows the data transition and sampling edges of SCK.

Figure 7-22 SPI DATA Format

A valid transfer requires a non-zero integer multiple of 16 SCK cycles (16, 32, 48, and so forth). If SSN is pulsed low and no SCK pulses are issued before SSN rises, a SPI error is reported. Similarly, if SSN is raised before the 16th rising edge of SCK, the transfer is aborted and a SPI error is reported. If SSN is held low after the 16th falling edge of SCK and additional SCK edges occur, the data continues to flow through the TPS92682-Q1 shift register and out of the MISO pin. When SSN transitions from low-to-high, the internal digital block decodes the most recent 16 bits that were received prior to the SSN rising edge.

SSN must transition to high after a multiple of 16 SCK cycles for a transaction to be valid and does not set the SPI error bit. In the case of a write transaction, the TPS92682-Q1 logic performs the requested operation when SSN transitions high. In the case of a read transaction, the read data is output during the next frame, regardless of whether a SPI error has occurred.

The data bit on MOSI is shifted into an internal 16-bit shift register (MS-bit first) while data is simultaneously shifted out of the MISO pin. While SSN is high (bus idle), MISO is tri-stated by the open-drain driver. While SSN is low, MISO is driven according to the 16-bit data pattern being shifted out based on the prior received command. At the falling edge of the SSN, to begin a new transaction, MISO is driven with the MS-bit of the outbound data, and is updated on each subsequent falling edge of SCK.