SLUSCX8 Data sheet

SLUSCX8C March 2019 – March 2021 TPS92682-Q1

PRODUCTION DATA

Package Options

Mechanical Data (Package|Pins)

DAP|32
- MPDS380A
RHB|32
- MPQF130D
RHM|32
- MPQF152B

Thermal pad, mechanical data (Package|Pins)

DAP|32
- PPTD363
RHB|32
- QFND644
RHM|32
- QFND588

Orderable Information

7.4.2 Normal Operation

In Normal operation mode, the registers can be programmed and the channels can be turned on. To operate in this mode, the LH pin must be low. The state machine for this mode is shown in Figure 7-20 and Figure 7-21.

Note:

The operational mode shown in Figure 7-20 and Figure 7-21 is only intended to describe the operation of the internal state machine and is not meant to be used as a guideline for the firmware development.

State 0: After POR, all the registers are reset to their default values, and the two channels are off.
State 1 (CHx_EN-BIT = 0): In this state, the device registers are ready to be programmed. Read FLT1 and FLT2 registers to clear all the fault read bits and the PC bit. Set the FPINRST bit in the EN register in order for the fault pins to be cleared. All the initializations must be completed before turning on the channels. The device stays in state-1 unless the condition of CHx_IADJ > 8 is met.
State 2 (CHx_EN-BIT = 1): The device advances to state-2 when the CHx_EN bit is set to "1". In this state, all the necessary conditions for initiating the soft-start ramp are checked. The CHx_complow signal and CHx_PWM are high, and the condition of CHx_IADJ > 8 is met. If a latched fault occurs in this state, the CHx_comp pin is pulled low, the CHx_EN bits are set to zero and the device returns to state-1. For a non-latched fault, the device remains in this mode until the fault is removed.
State 3 (SSDAC_RAMP): The SSDAC_RAMP state begins when all the conditions for the soft-start ramp initialization are met. In this state, the soft-start ramp DAC increments only when CHx_PWM is high. For CHx_PWM = LOW, the ramp is held constant. The DAC ramp re-starts the increment from the previous value at the next PWM dimming cycle, and when CHx_PWM = HIGH. If a latched-fault occurs in this state, the CHx_comp pin is pulled low, the CHx_EN bit is set to zero, and the device returns to state-1. For a non-latched fault, the associated channel is turned off, the CHx_comp pin is pulled low and the device returns to state-2. At the end of the soft-start ramp, read the FLT1 and FLT2 registers and set the FPINRST bit in the EN register in order for the fault read-bits and the fault pins to be cleared.

Figure 7-20 Operational Mode, States 0 and 1

Figure 7-21 Operational Mode, States 2 and 3