The TPS92691/-Q1 is a versatile LED controller that can support a range of step-up or step-down driver topologies. The device implements a fixed-frequency peak current mode control technique with programmable switching frequency, slope compensation, and soft-start timing. It incorporates a high voltage (65-V) rail-to-rail current sense amplifier that can directly measure LED current using either a high-side or a low-side series sense resistor. The amplifier is designed to achieve low input offset voltage and attain better than ±3% LED current accuracy over junction temperature range of 25°C to 140°C and output common-mode voltage range of 0 to 60 V.
LED current can be independently modulated using either analog or PWM dimming techniques. Linear analog dimming response with 15:1 range is obtained by varying the voltage from 140 mV to 2.25 V across the high impedance analog adjust (IADJ) input. PWM dimming of LED current is achieved by modulating the PWM input pin with the desired duty cycle and frequency. Optional DDRV gate driver output can be used to enable series FET dimming functionality to get over 1000:1 contrast ratio.
The TPS92691/-Q1 supports continuous LED status check through the current monitor (IMON) output. This allows for LED short circuit or open circuit detection and protection. Additional fault protection features include VCC UVLO, output OVP, switch cycle-by-cycle current limit, and thermal protection.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TPS92691-Q1 TPS92691 |
HTSSOP (16) | 5.10 mm × 6.60 mm |
DATE | REVISION | NOTES |
---|---|---|
December 2015 | * | Initial release. |
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1 | VIN | — | Input supply for the internal VCC regulator. Bypass with 100-nF capacitor to GND located close to the controller. |
2 | SS | I/O | Soft-start programming pin. Connect a capacitor to AGND to extend the start-up time. Switching can be disabled by shorting the pin to GND. |
3 | RT/SYNC | I/O | Oscillator frequency programming pin. Connect a resistor to AGND to set the switching frequency. The internal oscillator can be synchronized by coupling an external clock pulse through 100-nF series capacitor. |
4 | PWM | I | PWM dimming input. Driving the pin below 2.3 V (typ), turns off switching, idles the oscillator, disconnects the COMP pin, and sets DDRV output to ground. The input signal duty cycle controls the average LED current through PWM dimming operation. Connect to VCC when not used for PWM dimming. |
5 | COMP | I/O | Transconductance error amplifier output. Connect compensation network to achieve desired closed-loop response. |
6 | IADJ | I | LED current reference input. Connecting pin to VCC with 100-kΩ series resistor sets internal reference voltage to 2.42 V and the current sense threshold, V(CSP-CSN)to 172 mV. The pin can be modulated by external voltage source from 0 V to 2.25 V to implement analog dimming. |
7 | IMON | O | LED current report pin. The LED current sensed by CSP/CSN input is reported as VIMON = 14 × ILED × Rcs. Bypass with a 1-nF ceramic capacitor to AGND. |
8 | AGND | — | Analog ground. Return for the internal voltage reference and analog circuit. Connect to circuit ground, GND, to complete return path. |
9 | CSN | I | Current sense amplifier negative input (–). Connect directly to the negative node of LED current sense resistor RCS). |
10 | CSP | I | Current sense amplifier positive input (+). Connect directly to the positive node of LED current sense resistor RCS). |
11 | DDRV | O | Series dimming FET gate driver output. Connect to gate of external N-channel MOSFET or a level-shift circuit with P-channel MOSFET to implement series FET PWM dimming. |
12 | OVP | I | Hysteretic overvoltage protection input. Connect resistor divider from output voltage to set OVP threshold and hysteresis. |
13 | PGND | — | Power ground connection pin for internal N-channel MOSFET gate drivers. Connect to circuit ground, GND, to complete return path. |
14 | IS | I | Switch current sense input. Connected to the switch current sense resistor, RIS, in the source of the N-channel MOSFET. |
15 | GATE | O | N-channel MOSFET gate driver output. Connect to gate of external switching N-channel MOSFET. |
16 | VCC | — | VCC bias supply pin. Locally decouple to PGND using a 2.2-µF to 4.7-µF ceramic capacitor located close to the controller. |
PowerPAD | — | The AGND and PGND pin must be connected to the exposed PowerPAD for proper operation. This PowerPAD must be connected to PCB ground plane using multiple vias for good thermal performance. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Input voltage | VIN, CSP, CSN | –0.3 | 65 | V |
IADJ, IS, PWM, RT/SYNC | –0.3 | 8.8 | V | |
OVP, SS | –0.3 | 5.5 | V | |
CSP to CSN(3), PGND | –0.3 | 0.3 | V | |
Output voltage(4) | VCC, GATE, DDRV | –0.3 | 8.8 | V |
COMP | –0.3 | 5.0 | V | |
Source current | IMON | — | 100 | µA |
GATE, DDRV (Pulsed <20 ns) | — | 500 | mA | |
Sink current | GATE, DDRV (Pulsed <20 ns) | — | 500 | mA |
Operating junction temperature, TJ | –40 | 140 | °C | |
Storage temperature, Tstg | 150 | °C |
VALUE | UNIT | ||||
---|---|---|---|---|---|
TPS92691-Q1 IN PWP (HTSSOP) PACKAGE | |||||
V(ESD) | Electrostatic discharge | Human-body model (HBM), per AEC Q100-002, all pins(1) | ±2000 | V | |
Charged-device model (CDM), per AEC Q100-011 | All pins except 1, 8, 9, and 16 | ±500 | |||
Pins 1, 8, 9, and 16 | ±750 | ||||
TPS92691 IN PWP (HTSSOP) PACKAGE | |||||
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(2) | ±2000 | V | |
Charged-device model (CDM), per JEDEC specification JESD22-C101, all pins(3) | ±500 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
VIN | Supply input voltage | 6.5 | 14 | 65 | V |
VIN, crank | Supply input, battery crank voltage | 4.5 | V | ||
VCSP, VCSN | Current sense common mode | 0 | 60 | V | |
ƒSW | Switching frequency | 80 | 700 | kHz | |
ƒSYNC | SYNC frequency | 0.8 × ƒsw | 1.2 × ƒSW | kHz | |
VIADJ | Current reference voltage | 0.14 | VIADJ(CLAMP) | V | |
TA | Operating ambient temperature | –40 | 125 | °C |
THERMAL METRIC(1) | TPS92691/-Q1 | UNIT | |
---|---|---|---|
PWP (HTSSOP) | |||
16 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 40.8 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 26.1 | °C/W |
RθJB | Junction-to-board thermal resistance | 22.2 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.8 | °C/W |
ψJB | Junction-to-board characterization parameter | 22.0 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 2.3 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
INPUT VOLTAGE (VIN) | ||||||
VDO | LDO dropout voltage | ICC = 20 mA, VIN = 5 V | 300 | mV | ||
BIAS SUPPLY (VCC) | ||||||
VCC(REG) | Regulation voltage | No load | 7.0 | 7.5 | 8.0 | V |
VCC(UVLO) | Supply undervoltage protection | VCC rising threshold, VIN = 8 V | 4.1 | 4.35 | V | |
VCC falling threshold, VIN = 8 V | 3.75 | 4.0 | V | |||
Hysteresis | 100 | mV | ||||
ICC(LIMIT) | Supply current limit | VCC = 0 V | 26 | 38 | 46 | mA |
ICC(STBY) | Supply stand-by current | VPWM = 0 V | 1.8 | 2.1 | mA | |
ICC(SW) | Supply switching current | VCC = 7.5 V, CGATE = 1 nF | 5.1 | 6.6 | mA | |
OSCILLATOR (RT/SYNC) | ||||||
ƒSW | Switching frequency | RT = 40 kΩ | 165 | 200 | 230 | kHz |
RT = 20 kΩ | 327 | 390 | 448 | kHz | ||
VRT | RT output voltage | 1 | V | |||
VSYNC | SYNC rising threshold | VRT/SYNC rising | 2.7 | 3.1 | V | |
SYNC falling threshold | VRT/SYNC falling | 1.8 | 2 | V | ||
tSYNC(MIN) | Minimum SYNC clock pulse width | 100 | ns | |||
GATE DRIVER (GATE) | ||||||
RGH | Gate driver high side resistance | IGATE = –10 mA | 5.4 | 11.2 | Ω | |
RGL | Gate driver low side resistance | IGATE = 10 mA | 4.3 | 10.5 | Ω | |
CURRENT SENSE (IS) | ||||||
VIS(LIMIT) | Current limit threshold | 497 | 525 | 550 | mV | |
tIS(BLANK) | Leading edge blanking time | 103 | 150 | 188 | ns | |
tIS(FAULT) | Current limit fault time | 35 | µs | |||
tILMT(DLY) | IS to GATE propagation delay | VIS pulsed from 0 to 1 V | 100 | ns | ||
PWM COMPARATOR AND SLOPE COMPENSATION | ||||||
DMAX | Maximum duty cycle | 90.4% | 93% | 94.7% | ||
VLV | IS to COMP level shift voltage | No slope compensation added | 1.17 | 1.5 | 1.8 | V |
VSL | Slope compensation | D = DMAX (with max slope compensation) | 200 | mV | ||
ILV | IS level shift bias current | No slope compensation added | 25 | µA | ||
ILV + ISL | IS level shift source current | D = DMAX (with max slope compensation) | 115 | µA | ||
CURRENT SENSE AMPLIFIER (CSP, CSN) | ||||||
VCS(offset) | Cumulative offset voltage at VCSP = 60 V and V(CSP-CSN) = 150 mV, referred to current sense input | –40°C ≤ TJ ≤ 140°C | –5.2 | 5.9 | mV | |
25°C ≤ TJ ≤ 140°C | –4.4 | 4.6 | mV | |||
Cumulative offset voltage at VCSP = 60 V and V(CSP-CSN) = 10 mV, referred to current sense input | –40°C ≤ TJ ≤ 140°C | –3.5 | 5.0 | mV | ||
25°C ≤ TJ ≤ 140°C | -2.8 | 4.0 | mV | |||
Cumulative offset voltage at VCSN = 0 V and V(CSP-CSN) = 150 mV, referred to current sense input | –40°C ≤ TJ ≤ 140°C | –5.9 | 6.7 | mV | ||
25°C ≤ TJ ≤ 140°C | -4.7 | 5.0 | mV | |||
Cumulative offset voltage at VCSN = 0 V and V(CSP-CSN) = 10 mV, referred to current sense input | –40°C ≤ TJ ≤ 140°C | –2.3 | 3.2 | mV | ||
25°C ≤ TJ ≤ 140°C | –1.7 | 2.6 | mV | |||
CS(BW) | Current sense unity gain bandwidth | 500 | kHz | |||
ICS(BIAS) | CSP, CSN bias current | VCSP, CSN = 60 V | 4 | µA | ||
CURRENT MONITOR (IMON) | ||||||
VIMON(CLP) | IMON output voltage clamp | 3.2 | 3.7 | 4.2 | V | |
VIMON(OS) | IMON buffer offset voltage | –11.4 | –1.6 | 7.3 | mV | |
ANALOG ADJUST (IADJ) | ||||||
VIADJ(CLP) | IADJ internal clamp voltage | IIADJ = 1 µA | 2.27 | 2.42 | 2.55 | V |
IIADJ(BIAS) | IADJ input bias current | VIADJ < 2.2 V | 90 | nA | ||
RIADJ(LMT) | IADJ current limiting series resistor | VIADJ > 2.6 V | 12 | kΩ | ||
ERROR AMPLIFIER (COMP) | ||||||
gM | Transconductance | 121 | µA/V | |||
ICOMP(SRC) | COMP current source capacity | VIADJ = 1.4 V, V(CSP-CSN) = 0 V | 130 | µA | ||
ICOMP(SINK) | COMP current sink capacity | VIADJ = 0 V, V(CSP-CSN) = 0.1 V | 130 | µA | ||
EA(BW) | Error amplifier bandwidth | –3 dB | 5 | MHz | ||
VCOMP(RST) | COMP pin reset voltage | 100 | mV | |||
RCOMP(DCH) | COMP discharge FET resistance | 246 | Ω | |||
SOFT-START (SS) | ||||||
ISS | Soft-start source current | 7 | 10 | 12.8 | µA | |
VSS(RST) | Soft-start pin reset voltage | 25 | mV | |||
RSS(DCH) | SS discharge FET resistance | 260 | Ω | |||
OVERVOLTAGE PROTECTION (OVP) | ||||||
VOVP(THR) | OVP detection threshold | 1.18 | 1.24 | 1.31 | V | |
IOVP(HYS) | OVP hysteresis current | 12 | 20 | 27.5 | µA | |
PWM INPUT (PWM) | ||||||
VPWM(HIGH) | Schmitt trigger logic level (high threshold) | 2.5 | 2.7 | V | ||
VPWM(LOW) | Schmitt trigger logic level (low threshold) | 2.0 | 2.3 | V | ||
RPWM(PD) | PWM pulldown resistance | 1 | MΩ | |||
tDLY(RISE) | PWM to DDRV rising delay | 54 | ns | |||
tDLY(FALL) | PWM to DDRV falling delay | 72 | ns | |||
PWM GATE DRIVE OUTPUT (DDRV) | ||||||
RDH | DDRV high-side resistance | 6.1 | 12.8 | Ω | ||
RDL | DDRV low-side resistance | 5.2 | 11.4 | Ω | ||
THERMAL SHUTDOWN | ||||||
Thermal shutdown temperature | 175 | °C | ||||
Thermal shutdown hysteresis | 25 | °C |
VIADJ = 2.1 V |
VIADJ = 2.1 V |