SLVSDD9 March   2017 TPS92692 , TPS92692-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Internal Regulator and Undervoltage Lockout (UVLO)
      2. 7.3.2  Oscillator
      3. 7.3.3  Spread Spectrum Frequency Modulation
      4. 7.3.4  Gate Driver
      5. 7.3.5  Rail-to-Rail Current Sense Amplifier
      6. 7.3.6  Transconductance Error Amplifier
      7. 7.3.7  Switch Current Sense
      8. 7.3.8  Slope Compensation
      9. 7.3.9  Analog Adjust Input
      10. 7.3.10 DIM/PWM Input
      11. 7.3.11 Series P-Channel FET Dimming Gate Driver Output
      12. 7.3.12 Soft-Start
      13. 7.3.13 Current Monitor Output
      14. 7.3.14 Output Overvoltage Protection
      15. 7.3.15 Output Short-circuit Protection
      16. 7.3.16 Thermal Protection
      17. 7.3.17 Fault Indicator (FLT)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Hiccup Mode Short-circuit Protection
      2. 7.4.2 Fault Indication Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Duty Cycle Considerations
      2. 8.1.2  Inductor Selection
      3. 8.1.3  Output Capacitor Selection
      4. 8.1.4  Input Capacitor Selection
      5. 8.1.5  Main Power MOSFET Selection
      6. 8.1.6  Rectifier Diode Selection
      7. 8.1.7  LED Current Programming
      8. 8.1.8  Switch Current Sense Resistor
      9. 8.1.9  Slope Compensation
      10. 8.1.10 Feedback Compensation
      11. 8.1.11 Soft-Start
      12. 8.1.12 Overvoltage and Undervoltage Protection
      13. 8.1.13 Analog to PWM Dimming Considerations
      14. 8.1.14 Direct PWM Dimming Considerations
      15. 8.1.15 Series P-Channel MOSFET Selection
    2. 8.2 Typical Applications
      1. 8.2.1 Typical Boost LED Driver
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1  Calculating Duty Cycle
          2. 8.2.1.2.2  Setting Switching Frequency
          3. 8.2.1.2.3  Setting Dither Modulation Frequency
          4. 8.2.1.2.4  Inductor Selection
          5. 8.2.1.2.5  Output Capacitor Selection
          6. 8.2.1.2.6  Input Capacitor Selection
          7. 8.2.1.2.7  Main N-Channel MOSFET Selection
          8. 8.2.1.2.8  Rectifying Diode Selection
          9. 8.2.1.2.9  Programming LED Current
          10. 8.2.1.2.10 Setting Switch Current Limit
          11. 8.2.1.2.11 Programming Slope Compensation
          12. 8.2.1.2.12 Deriving Compensator Parameters
          13. 8.2.1.2.13 Setting Start-up Duration
          14. 8.2.1.2.14 Setting Overvoltage Protection Threshold
          15. 8.2.1.2.15 Analog-to-PWM Dimming Considerations
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Typical Buck-Boost LED Driver
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1  Calculating Duty Cycle
          2. 8.2.2.2.2  Setting Switching Frequency
          3. 8.2.2.2.3  Setting Dither Modulation Frequency
          4. 8.2.2.2.4  Inductor Selection
          5. 8.2.2.2.5  Output Capacitor Selection
          6. 8.2.2.2.6  Input Capacitor Selection
          7. 8.2.2.2.7  Main N-Channel MOSFET Selection
          8. 8.2.2.2.8  Rectifier Diode Selection
          9. 8.2.2.2.9  Programming LED Current
          10. 8.2.2.2.10 Setting Switch Current Limit and Slope Compensation
          11. 8.2.2.2.11 Programming Slope Compensation
          12. 8.2.2.2.12 Deriving Compensator Parameters
          13. 8.2.2.2.13 Setting Startup Duration
          14. 8.2.2.2.14 Setting Overvoltage Protection Threshold
          15. 8.2.2.2.15 Direct PWM Dimming Consideration
        3. 8.2.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Related Links
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

  • The performance of the switching regulator depends as much on the layout of the PCB as the component selection. Following a few simple guidelines will maximize noise rejection and minimize the generation of EMI within the circuit.
  • Discontinuous currents are the most likely to generate EMI. Therefore, take care when routing these paths. The main path for discontinuous current in the devices using a buck regulator topology contains the input capacitor, CIN, the recirculating diode, D, the N-channel MOSFET, Q1, and the sense resistor, RIS. In the TPS92692 and TPS92692-Q1 devices using a boost regulator topology, the discontinuous current flows through the output capacitor COUT, diode, D, N-channel MOSFET, Q1, and the current sense resistor, RIS. In devices using a buck-boost regulator topolog. Be careful when laying out both discontinuous loops. Ensure that these loops are as small as possible. In order to minimize parasitic inductance, ensure that the connection between all the components are short and thick. In particular, make the switch node (where L, D, and Q1 connect) just large enough to connect the components. To minimize excessive heating, large copper pours can be placed adjacent to the short current path of the switch node.
  • Route the CSP and CSN together with Kelvin connections to the current sense resistor with traces as short as possible. If needed, use common mode and differential mode noise filters to attenuate switching and diode reverse recovery noise from affecting the internal current sense amplifier.
  • Because the COMP, IS, OV, DIM/PWM, and IADJ pins are all high-impedance inputs that couple external noise easily, ensure that the loops containing these nodes are minimized whenever possible.
  • In some applications, the LED or LED array can be far away from the TPS92692 and TPS92692-Q1 devices, or on a separate PCB connected by a wiring harness. When an output capacitor is used and the LED array is large or separated from the rest of the regulator, place the output capacitor close to the LEDs to reduce the effects of parasitic inductance on the AC impedance of the capacitor.
  • The TPS92692 and TPS92692-Q1 devices have an exposed thermal pad to aid power dissipation. Adding several vias under the exposed pad helps conduct heat away from the device. The junction-to-ambient thermal resistance varies with application. The most significant variables are the area of copper in the PCB and the number of vias under the exposed pad. The integrity of the solder connection from the device exposed pad to the PCB is critical. Excessive voids greatly decrease the thermal dissipation capacity.

10.2 Layout Example

TPS92692 TPS92692-Q1 Layout_SLVSDD9.gif Figure 59. Layout Recommendation