SLVSFU7B July   2022  – April 2024 TPS929240-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Device Bias and Power
        1. 6.3.1.1 Power Bias (VBAT)
        2. 6.3.1.2 5V Low-Drop-Out Linear Regulator (VLDO)
        3. 6.3.1.3 Undervoltage Lockout (UVLO) and Power-On-Reset (POR)
        4. 6.3.1.4 Power Supply (SUPPLY)
        5. 6.3.1.5 Programmable Low Supply Warning
      2. 6.3.2 Constant Current Output
        1. 6.3.2.1 Reference Current with External Resistor (REF)
        2. 6.3.2.2 64-Step Programmable High-Side Constant-Current Output
      3. 6.3.3 PWM Dimming
        1. 6.3.3.1 PWM Generator
        2. 6.3.3.2 PWM Dimming Frequency
        3. 6.3.3.3 Blank Time
        4. 6.3.3.4 Phase Shift PWM Dimming
        5. 6.3.3.5 Linear Brightness Control
        6. 6.3.3.6 Exponential Brightness Control
      4. 6.3.4 FAIL-SAFE State Operation
      5. 6.3.5 On-Chip, 8-Bit, Analog-to-Digital Converter (ADC)
        1. 6.3.5.1 Minimum On Time for ADC Measurement
        2. 6.3.5.2 ADC Auto Scan
        3. 6.3.5.3 ADC Error
      6. 6.3.6 Diagnostic and Protection in NORMAL State
        1. 6.3.6.1  VBAT Undervoltage Lockout Diagnostics in NORMAL state
        2. 6.3.6.2  Low-Supply Warning Diagnostics in NORMAL State
        3. 6.3.6.3  Supply Undervoltage Diagnostics in NORMAL State
        4. 6.3.6.4  Reference Diagnostics in NORMAL state
        5. 6.3.6.5  Pre-Thermal Warning in NORMAL state
        6. 6.3.6.6  Overtemperature Protection in NORMAL state
        7. 6.3.6.7  Overtemperature Shutdown in NORMAL state
        8. 6.3.6.8  LED Open-Circuit Diagnostics in NORMAL state
        9. 6.3.6.9  LED Short-Circuit Diagnostics in NORMAL state
        10. 6.3.6.10 Single-LED Short-Circuit Detection in NORMAL state
        11. 6.3.6.11 EEPROM CRC Error in NORMAL state
        12. 6.3.6.12 Communication Loss Diagnostic in NORMAL State
        13. 6.3.6.13 Fault Masking in NORMAL state
        14.       53
      7. 6.3.7 Diagnostic and Protection in FAIL-SAFE states
        1. 6.3.7.1  Supply Undervoltage Lockout Diagnostics in FAIL-SAFE states
        2. 6.3.7.2  Low-Supply Warning Diagnostics in FAIL-SAFE states
        3. 6.3.7.3  Supply Undervoltage Diagnostics in FAIL-SAFE State
        4. 6.3.7.4  Reference Diagnostics in FAIL-SAFE states
        5. 6.3.7.5  Pre-Thermal Warning in FAIL-SAFE state
        6. 6.3.7.6  Overtemperature Protection in FAIL-SAFE state
        7. 6.3.7.7  Overtemperature Shutdown in FAIL-SAFE state
        8. 6.3.7.8  LED Open-Circuit Diagnostics in FAIL-SAFE state
        9. 6.3.7.9  LED Short-Circuit Diagnostics in FAIL-SAFE state
        10. 6.3.7.10 Single-LED Short-Circuit Detection in FAIL-SAFE state
        11. 6.3.7.11 EEPROM CRC Error in FAIL-SAFE State
        12. 6.3.7.12 Fault Masking in FAIL-SAFE state
        13.       Diagnostics Table in FAIL-SAFE State
      8. 6.3.8 OFAF Setup In FAIL-SAFE state
      9. 6.3.9 ERR Output
    4. 6.4 Device Functional Modes
      1. 6.4.1 POR State
      2. 6.4.2 INITIALIZATION state
      3. 6.4.3 NORMAL state
      4. 6.4.4 FAIL-SAFE state
      5. 6.4.5 PROGRAM state
    5. 6.5 Programming
      1. 6.5.1 FlexWire Protocol
        1. 6.5.1.1 Protocol Overview
        2. 6.5.1.2 UART Interface Address Setting
        3. 6.5.1.3 Status Response
        4. 6.5.1.4 Synchronization Byte
        5. 6.5.1.5 Device Address Byte
        6. 6.5.1.6 Register Address Byte
        7. 6.5.1.7 Data Frame
        8. 6.5.1.8 CRC Frame
        9. 6.5.1.9 Burst Mode
      2. 6.5.2 Registers Lock
      3. 6.5.3 Register Default Data
      4. 6.5.4 EEPROM Programming
        1. 6.5.4.1 Chip Selection by Pulling REF Pin High
        2. 6.5.4.2 Chip Selection by ADDR Pins Configuration
        3. 6.5.4.3 EEPROM Register Access and Burn
        4. 6.5.4.4 EEPROM PROGRAM State Exit
    6. 6.6 Register Maps
      1. 6.6.1 BRT Registers
      2. 6.6.2 IOUT Registers
      3. 6.6.3 CONF Registers
      4. 6.6.4 CTRL Registers
      5. 6.6.5 FLAG Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Smart Rear Lamp with Distributed LED Drivers
      2. 7.2.2 Design Requirements
      3. 7.2.3 Detailed Design Procedure
      4. 7.2.4 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DCP|38
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.2.3 Detailed Design Procedure

STEP 1: Determine the architecture at system level.

Because MCU is located in a separate board, the CAN physical layer must be used for off-board long distance communication between LED driver boards and MCU board. The overall system block diagram is shown in Figure 7-1 and the typical schematic for 48 strings of LED board is shown in Figure 7-2. The pullup resistors for RX and TX interface can or cannot required, depending on the model of the CAN transceiver. Normally the pullup resistor value for RX and TX must be about 10kΩ. TI recommends putting a 4.7µF ceramic capacitor on the VLDO output to keep the voltage stable. Because only one CAN transceiver is required per one PCB board, the CAN transceiver must only be powered by one LDO output of the TPS929240-Q1. Do not tie the LDO outputs for all TPS929240-Q1 in one PCB board. TI also recommends placing a 4.7µF decoupling ceramic capacitor close to the VBAT and the SUPPLY pin of each TPS929240-Q1 to obtain good EMC performance.

STEP 2: Thermal analysis for the worst application conditions.

Normally the thermal analysis is necessary for linear LED-driver applications to ensure that the operation junction temperature of TPS929240-Q1 is well managed. The total power consumption on the TPS929240-Q1 itself is one important factor determining operation junction temperature, and it can be calculated by using the following equation.

Equation 9. GUID-FBDA0EDB-726E-4606-9F02-C63A9E06F4B8-low.gif

where

  • V(SPPLY_MAX) is maximum supply voltage.
  • V(LED_MIN) is minimum output voltage.
  • I(CH) is channel current.
  • N(CH) is number of used channels.

Based on the worst-case analysis for maximum power consumption on device, either optimizing PCB layout for better power dissipation as Layout Example describes or implementing a DC-to-DC converter in previous stage on MCU board can be considered. The DC-to-DC such as a buck converter or buck-boost converter can regulate the battery voltage to be a stable supply for the TPS929240-Q1 with sufficient headroom. A properly designed supply voltage is helpful to minimize the power consumption on the TPS929240-Q1 itself as well as the whole system. In this application, the DC-to-DC converter with 8.6V output voltage can make sure current output on each output channel of TPS929240-Q1 is stable. The calculated maximum power dissipation on the device is 2.04 W as show in the below equation.

Equation 10. GUID-20230404-SS0I-2XQ3-GBJH-TPXMHXDBNZLV-low.svg

where

  • V(SPPLY_MAX) is maximum supply voltage.
  • V(LED_MIN) is minimum output voltage.
  • I(CH) is channel current.
  • N(CH) is number of used channels.

STEP 3: Set up the slave address for individual TPS929240-Q1.

The slave address of TPS929240-Q1 can be configured by ADDR2/ADDR1/ADDR0 pins or DEVADDR[3:0] selected by INTADDR. The detailed description is explained in UART Interface Address Setting. If the total number of TPS929240-Q1 is less than 8, TI recommends using ADDR2/ADDR1/ADDR0 pins for slave device configuration. If the total number of TPS929240-Q1 is bigger than 8, DEVADDR[3] code together with external inputs on ADDR2/ADDR1/ADDR0 can be used to support up to 16 devices on the same bus. The default value of DEVADDR[3] for TPS929240-Q1 is set to 0 and could be changed by the EEPROM burning. The detailed EEPROM burning flow is introduced in EEPROM Register Access and Burn . The default value of DEVADDR[3] for TPS929240A-Q1 is set to 1 and can be used with TPS929240-Q1 to achieve maximum 16 devices on one FlexWire bus.

STEP 4: DC current setup for each LED string.

The DC current for all output channel can be programmed by an external resistor, R(REF), and internal register REFRANGE. The resistor value can be calculated by using Equation 11. The manufacturer default value for K(REF) is 512. If the other number rather than 512 is chosen for DC current setting, the selected code needs to be burnt into EEPROM to change the default value for REFRANGE. A 1nF ceramic capacitor is recommended to be placed in parallel with R(REF) resistor to improve the noise immunity. The 6-bit register IOUTXn can be used to program DC current for each output channel independently mainly for dot correction purpose. The code setting for IOUTXn registers must be decided in the end of production line according to the LED calibration result. The detailed calculation is described in 64-Step Programmable High-Side Constant-Current Output.

Equation 11. GUID-5F34E69B-A241-4FB1-AC0A-6BE19BE82B3F-low.gif

where

  • V(REF) = 1.235V typically.
  • K(REF) = 64, 128, 256 or 512 (default).
Table 7-1 Reference Current Range Setting
CURRENT (mA) REFRANGE K(REF) REF RESISTOR VALUE (kΩ)
50 11b 512 12.7
10b 256 6.34
01b 128 3.16
00b 64 1.58

TI recommends placing a 1nF ceramic capacitor on each of output channels to achieve good EMC performance.

STEP 5: Design the configuration for PWM generator. Basically, there are three main parameters for PWM generator that must be considered, including:

  • PWM frequency is set by PWMFREQ. The detailed calculation and description is explained in PWM Dimming Frequency. The default value of PWMFREQ can be changed by burning the target value to EEPROM.
  • PWM duty cycle is set by PWMOUTXn and PWMLOWOUTXn. The detailed calculation and description are explained in Linear Brightness Control. The default value of PWMOUTXn and PWMLOWOUTXn can be changed by burning the target value to EEPROM.
  • PWM dimming method set by EXPEN. The detailed calculation and description are explained in Exponential Brightness Control. The default value of EXPEN can be changed by burning the target value to EEPROM.

STEP 6: Design the diagnostics configuration. The diagnostics configuration for both NORMAL state and FAIL-SAFE states must be set up properly based on the system requirements. The following configuration registers must be designed:

  • Low-supply warning threshold set by LOWSUPTH. The detail calculation and description are explained in Low-Supply Warning Diagnostics in NORMAL State. The default value of LOWSUPTH can be changed by burning the target value to EEPROM.
  • Diagnostics enabling setup for each channel by CONF_DIAGENCHx. The diagnostics for each channel can be enabled or disabled by DIAGENOUTXn register. The detailed description is explained in Fault Masking. The default value of DIAGENOUTXn can be changed by burning the target value to EEPROM.
  • Single-LED short-circuit configuration by SLSEN, SLSTHOUTXn, SLSTH0 and SLSTH1. The detailed calculation and description are explained in Single-LED Short-Circuit Detection in NORMAL state. The default value of SLSEN, SLSTHOUTXn, SLSTH0 and SLSTH1 can be changed by burning the target value to EEPROM.
  • FAIL-SAFE state access watchdog timer setup by WDTIMER. The detailed calculation and description are explained in NORMAL state. The default value of WDTIMER can be changed by burning the target value to EEPROM.
  • Channel setup in FAIL-SAFE state. In FAIL-SAFE state, the FS pin can be used as control signal to turn on or turn off the corresponding channel. Each current output channel has its own register, FSOUTXn to set the mapping to FS0 or FS1. When FSOUTXn is set to 0, the corresponding current output channel is controlled by FS0 input, otherwise it is controlled by FS1 input. The detailed calculation and description are explained in FAIL-SAFE State Operation.
  • One-fails-all-fail setup by OFAF. If the one-fails-all-fail can be enabled by burning 1 to OFAF according to system requirements. Tie the ERR pins for all TPS929240-Q1 in the system together with a single 4.7kΩ pullup resistor to realize the one-fails-all-fail feature. The detailed calculation and description is explained in OFAF Setup In FAIL-SAFE State.
  • CRC check reference calculation for EEPCRC. After all the EEPROM register values are designed, the CRC reference value for all EEPROM register must be calculated and burnt into EEPCRC. The detailed calculation and description are explained in EEPROM CRC Error in NORMAL state.

STEP 7: EEPROM burning solution design.

TI recommends that the EEPROM burning be done in the end of production line. The detailed flow is introduced in EEPROM Register Access and Burn .