SLVSFU7B July   2022  – April 2024 TPS929240-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Device Bias and Power
        1. 6.3.1.1 Power Bias (VBAT)
        2. 6.3.1.2 5V Low-Drop-Out Linear Regulator (VLDO)
        3. 6.3.1.3 Undervoltage Lockout (UVLO) and Power-On-Reset (POR)
        4. 6.3.1.4 Power Supply (SUPPLY)
        5. 6.3.1.5 Programmable Low Supply Warning
      2. 6.3.2 Constant Current Output
        1. 6.3.2.1 Reference Current with External Resistor (REF)
        2. 6.3.2.2 64-Step Programmable High-Side Constant-Current Output
      3. 6.3.3 PWM Dimming
        1. 6.3.3.1 PWM Generator
        2. 6.3.3.2 PWM Dimming Frequency
        3. 6.3.3.3 Blank Time
        4. 6.3.3.4 Phase Shift PWM Dimming
        5. 6.3.3.5 Linear Brightness Control
        6. 6.3.3.6 Exponential Brightness Control
      4. 6.3.4 FAIL-SAFE State Operation
      5. 6.3.5 On-Chip, 8-Bit, Analog-to-Digital Converter (ADC)
        1. 6.3.5.1 Minimum On Time for ADC Measurement
        2. 6.3.5.2 ADC Auto Scan
        3. 6.3.5.3 ADC Error
      6. 6.3.6 Diagnostic and Protection in NORMAL State
        1. 6.3.6.1  VBAT Undervoltage Lockout Diagnostics in NORMAL state
        2. 6.3.6.2  Low-Supply Warning Diagnostics in NORMAL State
        3. 6.3.6.3  Supply Undervoltage Diagnostics in NORMAL State
        4. 6.3.6.4  Reference Diagnostics in NORMAL state
        5. 6.3.6.5  Pre-Thermal Warning in NORMAL state
        6. 6.3.6.6  Overtemperature Protection in NORMAL state
        7. 6.3.6.7  Overtemperature Shutdown in NORMAL state
        8. 6.3.6.8  LED Open-Circuit Diagnostics in NORMAL state
        9. 6.3.6.9  LED Short-Circuit Diagnostics in NORMAL state
        10. 6.3.6.10 Single-LED Short-Circuit Detection in NORMAL state
        11. 6.3.6.11 EEPROM CRC Error in NORMAL state
        12. 6.3.6.12 Communication Loss Diagnostic in NORMAL State
        13. 6.3.6.13 Fault Masking in NORMAL state
        14.       53
      7. 6.3.7 Diagnostic and Protection in FAIL-SAFE states
        1. 6.3.7.1  Supply Undervoltage Lockout Diagnostics in FAIL-SAFE states
        2. 6.3.7.2  Low-Supply Warning Diagnostics in FAIL-SAFE states
        3. 6.3.7.3  Supply Undervoltage Diagnostics in FAIL-SAFE State
        4. 6.3.7.4  Reference Diagnostics in FAIL-SAFE states
        5. 6.3.7.5  Pre-Thermal Warning in FAIL-SAFE state
        6. 6.3.7.6  Overtemperature Protection in FAIL-SAFE state
        7. 6.3.7.7  Overtemperature Shutdown in FAIL-SAFE state
        8. 6.3.7.8  LED Open-Circuit Diagnostics in FAIL-SAFE state
        9. 6.3.7.9  LED Short-Circuit Diagnostics in FAIL-SAFE state
        10. 6.3.7.10 Single-LED Short-Circuit Detection in FAIL-SAFE state
        11. 6.3.7.11 EEPROM CRC Error in FAIL-SAFE State
        12. 6.3.7.12 Fault Masking in FAIL-SAFE state
        13.       Diagnostics Table in FAIL-SAFE State
      8. 6.3.8 OFAF Setup In FAIL-SAFE state
      9. 6.3.9 ERR Output
    4. 6.4 Device Functional Modes
      1. 6.4.1 POR State
      2. 6.4.2 INITIALIZATION state
      3. 6.4.3 NORMAL state
      4. 6.4.4 FAIL-SAFE state
      5. 6.4.5 PROGRAM state
    5. 6.5 Programming
      1. 6.5.1 FlexWire Protocol
        1. 6.5.1.1 Protocol Overview
        2. 6.5.1.2 UART Interface Address Setting
        3. 6.5.1.3 Status Response
        4. 6.5.1.4 Synchronization Byte
        5. 6.5.1.5 Device Address Byte
        6. 6.5.1.6 Register Address Byte
        7. 6.5.1.7 Data Frame
        8. 6.5.1.8 CRC Frame
        9. 6.5.1.9 Burst Mode
      2. 6.5.2 Registers Lock
      3. 6.5.3 Register Default Data
      4. 6.5.4 EEPROM Programming
        1. 6.5.4.1 Chip Selection by Pulling REF Pin High
        2. 6.5.4.2 Chip Selection by ADDR Pins Configuration
        3. 6.5.4.3 EEPROM Register Access and Burn
        4. 6.5.4.4 EEPROM PROGRAM State Exit
    6. 6.6 Register Maps
      1. 6.6.1 BRT Registers
      2. 6.6.2 IOUT Registers
      3. 6.6.3 CONF Registers
      4. 6.6.4 CTRL Registers
      5. 6.6.5 FLAG Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Smart Rear Lamp with Distributed LED Drivers
      2. 7.2.2 Design Requirements
      3. 7.2.3 Detailed Design Procedure
      4. 7.2.4 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DCP|38
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5.4.1 Chip Selection by Pulling REF Pin High

The TPS929240-Q1 supports using REF pin as chip-select during EEPROM programming. Considering multiple TPS929240-Q1 devices connected on one FlexWire bus before burning EEPROM, the slave address for all TPS929240-Q1 are all same before programming in case internal EEPROM register DEVADDR is used for slave address setup. The EEPROM burning instruction can be sent to target TPS929240-Q1 by pulling the REF pin of the target TPS929240-Q1 to 5 V. After the REF pin is pulled up to 5 V, the TPS929240-Q1 ignores the device address setup by ADDR2/ADDR1/ADDR0 pins or EEPROM programmed device address in EEP_DEVADDR. The master controller must send out data to target TPS929240-Q1 with device address as 0h and not in broadcast mode.