DLPS202A
October 2020 – August 2024
TPS99000S-Q1
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Electrical Characteristics—Transimpedance Amplifier Parameters
5.6
Electrical Characteristics—Digital to Analog Converters
5.7
Electrical Characteristics—Analog to Digital Converter
5.8
Electrical Characteristics—FET Gate Drivers
5.9
Electrical Characteristics—Photo Comparator
5.10
Electrical Characteristics—Voltage Regulators
5.11
Electrical Characteristics—Temperature and Voltage Monitors
5.12
Electrical Characteristics—Current Consumption
5.13
Power-Up Timing Requirements
5.14
Power-Down Timing Requirements
5.15
Timing Requirements—Sequencer Clock
5.16
Timing Requirements—Host and Diagnostic Port SPI Interface
5.17
Timing Requirements—ADC Interface
5.18
Switching Characteristics
6
Detailed Description
6.1
Overview
6.2
Functional Block Diagram
6.3
Feature Description
6.3.1
Illumination Control
6.3.1.1
Illumination System High Dynamic Range Dimming Overview
6.3.1.2
Illumination Control Loop
6.3.1.3
Continuous Mode Operation
6.3.1.3.1
Output Capacitance in Continuous Mode
6.3.1.3.2
Continuous Mode Driver Distortion and Blanking Current
6.3.1.3.3
Continuous Mode S_EN2 Dissipative Load Shunt Options
6.3.1.3.4
Continuous Mode Constant OFF Time
6.3.1.3.5
Continuous Mode Current Limit
6.3.1.4
Discontinuous Mode Operation
6.3.1.4.1
Discontinuous Mode Pulse Width Limit
6.3.1.4.2
COMPOUT_LOW Timer in Discontinuous Operation
6.3.1.4.3
Dimming Within Discontinuous Operation Range
6.3.1.4.4
Multiple Pulse Heights to Increase Bit Depth
6.3.1.4.5
TIA Gain Adjustment
6.3.1.4.6
Current Limit in Discontinuous Mode
6.3.1.4.7
CMODE Big Cap Mode in Discontinuous Operation
6.3.2
Over-Brightness Detection
6.3.2.1
Photo Feedback Monitor BIST
6.3.2.2
Excessive Brightness BIST
6.3.3
Analog to Digital Converter
6.3.3.1
Analog to Digital Converter Input Table
6.3.4
Power Sequencing and Monitoring
6.3.4.1
Power Monitoring
6.3.5
DMD Mirror Voltage Regulator
6.3.6
Low Dropout Regulators
6.3.7
System Monitoring Features
6.3.7.1
Windowed Watchdog Circuits
6.3.7.2
Die Temperature Monitors
6.3.7.3
External Clock Ratio Monitor
6.3.8
Communication Ports
6.3.8.1
Serial Peripheral Interface (SPI)
6.4
Device Functional Modes
6.4.1
OFF
6.4.2
STANDBY
6.4.3
POWERING_DMD
6.4.4
DISPLAY_RDY
6.4.5
DISPLAY_ON
6.4.6
PARKING
6.4.7
SHUTDOWN
6.5
Register Maps
6.5.1
System Status Registers
6.5.2
ADC Control
6.5.3
General Fault Status
7
Application and Implementation
7.1
Application Information
7.2
Typical Applications
7.2.1
HUD
7.2.1.1
Design Requirements
7.2.1.2
Application Design Considerations
7.2.1.2.1
Photodiode Considerations
7.2.1.2.2
LED Current Measurement
7.2.1.2.3
Setting the Current Limit
7.2.1.2.4
Input Voltage Variation Impact
7.2.1.2.5
Discontinuous Mode Photo Feedback Considerations
7.2.1.2.6
Transimpedance Amplifiers (TIAs, Usage, Offset, Dark Current, Ranges, RGB Trim)
8
Power Supply Recommendations
8.1
TPS99000S-Q1 Power Supply Architecture
8.2
TPS99000S-Q1 Power Outputs
8.3
Power Supply Architecture
9
Layout
9.1
Layout Guidelines
9.1.1
Power/High Current Signals
9.1.2
Sensitive Analog Signals
9.1.3
High-Speed Digital Signals
9.1.4
High Power Current Loops
9.1.5
Kelvin Sensing Connections
9.1.6
Ground Separation
10
Device and Documentation Support
10.1
Device Support
10.1.1
Third-Party Products Disclaimer
10.2
Receiving Notification of Documentation Updates
10.3
Support Resources
10.4
Trademarks
10.5
Electrostatic Discharge Caution
10.6
Glossary
11
Revision History
12
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
PZP|100
MPQF053D
Thermal pad, mechanical data (Package|Pins)
PZP|100
PPTD102E
Orderable Information
dlps202a_oa
dlps202a_pm
5.17
Timing Requirements—ADC Interface
MIN
NOM
MAX
UNIT
t
ADCDINSETUP
ADC DIN to CLK Rising Setup Time
5
ns
t
ADCDINHOLD
ADC CLK Rising to DIN Hold Time
5
ns
t
ADCDOUT
CLK Rising to DOUT
0
15
ns