DLPS202A October   2020  – August 2024 TPS99000S-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics—Transimpedance Amplifier Parameters
    6. 5.6  Electrical Characteristics—Digital to Analog Converters
    7. 5.7  Electrical Characteristics—Analog to Digital Converter
    8. 5.8  Electrical Characteristics—FET Gate Drivers
    9. 5.9  Electrical Characteristics—Photo Comparator
    10. 5.10 Electrical Characteristics—Voltage Regulators
    11. 5.11 Electrical Characteristics—Temperature and Voltage Monitors
    12. 5.12 Electrical Characteristics—Current Consumption
    13. 5.13 Power-Up Timing Requirements
    14. 5.14 Power-Down Timing Requirements
    15. 5.15 Timing Requirements—Sequencer Clock
    16. 5.16 Timing Requirements—Host and Diagnostic Port SPI Interface
    17. 5.17 Timing Requirements—ADC Interface
    18. 5.18 Switching Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Illumination Control
        1. 6.3.1.1 Illumination System High Dynamic Range Dimming Overview
        2. 6.3.1.2 Illumination Control Loop
        3. 6.3.1.3 Continuous Mode Operation
          1. 6.3.1.3.1 Output Capacitance in Continuous Mode
          2. 6.3.1.3.2 Continuous Mode Driver Distortion and Blanking Current
          3. 6.3.1.3.3 Continuous Mode S_EN2 Dissipative Load Shunt Options
          4. 6.3.1.3.4 Continuous Mode Constant OFF Time
          5. 6.3.1.3.5 Continuous Mode Current Limit
        4. 6.3.1.4 Discontinuous Mode Operation
          1. 6.3.1.4.1 Discontinuous Mode Pulse Width Limit
          2. 6.3.1.4.2 COMPOUT_LOW Timer in Discontinuous Operation
          3. 6.3.1.4.3 Dimming Within Discontinuous Operation Range
          4. 6.3.1.4.4 Multiple Pulse Heights to Increase Bit Depth
          5. 6.3.1.4.5 TIA Gain Adjustment
          6. 6.3.1.4.6 Current Limit in Discontinuous Mode
          7. 6.3.1.4.7 CMODE Big Cap Mode in Discontinuous Operation
      2. 6.3.2 Over-Brightness Detection
        1. 6.3.2.1 Photo Feedback Monitor BIST
        2. 6.3.2.2 Excessive Brightness BIST
      3. 6.3.3 Analog to Digital Converter
        1. 6.3.3.1 Analog to Digital Converter Input Table
      4. 6.3.4 Power Sequencing and Monitoring
        1. 6.3.4.1 Power Monitoring
      5. 6.3.5 DMD Mirror Voltage Regulator
      6. 6.3.6 Low Dropout Regulators
      7. 6.3.7 System Monitoring Features
        1. 6.3.7.1 Windowed Watchdog Circuits
        2. 6.3.7.2 Die Temperature Monitors
        3. 6.3.7.3 External Clock Ratio Monitor
      8. 6.3.8 Communication Ports
        1. 6.3.8.1 Serial Peripheral Interface (SPI)
    4. 6.4 Device Functional Modes
      1. 6.4.1 OFF
      2. 6.4.2 STANDBY
      3. 6.4.3 POWERING_DMD
      4. 6.4.4 DISPLAY_RDY
      5. 6.4.5 DISPLAY_ON
      6. 6.4.6 PARKING
      7. 6.4.7 SHUTDOWN
    5. 6.5 Register Maps
      1. 6.5.1 System Status Registers
      2. 6.5.2 ADC Control
      3. 6.5.3 General Fault Status
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 HUD
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Application Design Considerations
          1. 7.2.1.2.1 Photodiode Considerations
          2. 7.2.1.2.2 LED Current Measurement
          3. 7.2.1.2.3 Setting the Current Limit
          4. 7.2.1.2.4 Input Voltage Variation Impact
          5. 7.2.1.2.5 Discontinuous Mode Photo Feedback Considerations
          6. 7.2.1.2.6 Transimpedance Amplifiers (TIAs, Usage, Offset, Dark Current, Ranges, RGB Trim)
  9. 8 Power Supply Recommendations
    1. 8.1 TPS99000S-Q1 Power Supply Architecture
    2. 8.2 TPS99000S-Q1 Power Outputs
    3. 8.3 Power Supply Architecture
  10. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 Power/High Current Signals
      2. 9.1.2 Sensitive Analog Signals
      3. 9.1.3 High-Speed Digital Signals
      4. 9.1.4 High Power Current Loops
      5. 9.1.5 Kelvin Sensing Connections
      6. 9.1.6 Ground Separation
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.16 Timing Requirements—Host and Diagnostic Port SPI Interface

MINNOMMAXUNIT
tSPICPERSPI CLK Cycle Time3133ns
tSPICHIGHSPI CLK High Time10ns
tSPICLOWSPI CLK Low Time10ns
tSPIDOUTCLK Falling to DOUT015ns
tSSSETUPSPI SS_Z to CLK Rising Setup Time5ns
tSSHOLDSPI CLK Rising to SS_Z Hold Time5ns
tDINSETUPSPI DIN to CLK Rising Setup Time5ns
tDINHOLDSPI CLK Rising to DIN Hold Time5ns
TPS99000S-Q1 DLPC23xS-Q1 Diagnostic Interface Timing Figure 5-4 DLPC23xS-Q1 Diagnostic Interface Timing
TPS99000S-Q1 Chip Select Setup and Hold Timing Figure 5-5 Chip Select Setup and Hold Timing