DLPS202A October   2020  – August 2024 TPS99000S-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics—Transimpedance Amplifier Parameters
    6. 5.6  Electrical Characteristics—Digital to Analog Converters
    7. 5.7  Electrical Characteristics—Analog to Digital Converter
    8. 5.8  Electrical Characteristics—FET Gate Drivers
    9. 5.9  Electrical Characteristics—Photo Comparator
    10. 5.10 Electrical Characteristics—Voltage Regulators
    11. 5.11 Electrical Characteristics—Temperature and Voltage Monitors
    12. 5.12 Electrical Characteristics—Current Consumption
    13. 5.13 Power-Up Timing Requirements
    14. 5.14 Power-Down Timing Requirements
    15. 5.15 Timing Requirements—Sequencer Clock
    16. 5.16 Timing Requirements—Host and Diagnostic Port SPI Interface
    17. 5.17 Timing Requirements—ADC Interface
    18. 5.18 Switching Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Illumination Control
        1. 6.3.1.1 Illumination System High Dynamic Range Dimming Overview
        2. 6.3.1.2 Illumination Control Loop
        3. 6.3.1.3 Continuous Mode Operation
          1. 6.3.1.3.1 Output Capacitance in Continuous Mode
          2. 6.3.1.3.2 Continuous Mode Driver Distortion and Blanking Current
          3. 6.3.1.3.3 Continuous Mode S_EN2 Dissipative Load Shunt Options
          4. 6.3.1.3.4 Continuous Mode Constant OFF Time
          5. 6.3.1.3.5 Continuous Mode Current Limit
        4. 6.3.1.4 Discontinuous Mode Operation
          1. 6.3.1.4.1 Discontinuous Mode Pulse Width Limit
          2. 6.3.1.4.2 COMPOUT_LOW Timer in Discontinuous Operation
          3. 6.3.1.4.3 Dimming Within Discontinuous Operation Range
          4. 6.3.1.4.4 Multiple Pulse Heights to Increase Bit Depth
          5. 6.3.1.4.5 TIA Gain Adjustment
          6. 6.3.1.4.6 Current Limit in Discontinuous Mode
          7. 6.3.1.4.7 CMODE Big Cap Mode in Discontinuous Operation
      2. 6.3.2 Over-Brightness Detection
        1. 6.3.2.1 Photo Feedback Monitor BIST
        2. 6.3.2.2 Excessive Brightness BIST
      3. 6.3.3 Analog to Digital Converter
        1. 6.3.3.1 Analog to Digital Converter Input Table
      4. 6.3.4 Power Sequencing and Monitoring
        1. 6.3.4.1 Power Monitoring
      5. 6.3.5 DMD Mirror Voltage Regulator
      6. 6.3.6 Low Dropout Regulators
      7. 6.3.7 System Monitoring Features
        1. 6.3.7.1 Windowed Watchdog Circuits
        2. 6.3.7.2 Die Temperature Monitors
        3. 6.3.7.3 External Clock Ratio Monitor
      8. 6.3.8 Communication Ports
        1. 6.3.8.1 Serial Peripheral Interface (SPI)
    4. 6.4 Device Functional Modes
      1. 6.4.1 OFF
      2. 6.4.2 STANDBY
      3. 6.4.3 POWERING_DMD
      4. 6.4.4 DISPLAY_RDY
      5. 6.4.5 DISPLAY_ON
      6. 6.4.6 PARKING
      7. 6.4.7 SHUTDOWN
    5. 6.5 Register Maps
      1. 6.5.1 System Status Registers
      2. 6.5.2 ADC Control
      3. 6.5.3 General Fault Status
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 HUD
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Application Design Considerations
          1. 7.2.1.2.1 Photodiode Considerations
          2. 7.2.1.2.2 LED Current Measurement
          3. 7.2.1.2.3 Setting the Current Limit
          4. 7.2.1.2.4 Input Voltage Variation Impact
          5. 7.2.1.2.5 Discontinuous Mode Photo Feedback Considerations
          6. 7.2.1.2.6 Transimpedance Amplifiers (TIAs, Usage, Offset, Dark Current, Ranges, RGB Trim)
  9. 8 Power Supply Recommendations
    1. 8.1 TPS99000S-Q1 Power Supply Architecture
    2. 8.2 TPS99000S-Q1 Power Outputs
    3. 8.3 Power Supply Architecture
  10. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 Power/High Current Signals
      2. 9.1.2 Sensitive Analog Signals
      3. 9.1.3 High-Speed Digital Signals
      4. 9.1.4 High Power Current Loops
      5. 9.1.5 Kelvin Sensing Connections
      6. 9.1.6 Ground Separation
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

TPS99000S-Q1 PZP Package100-Pin HTQFPTop ViewFigure 4-1 PZP Package100-Pin HTQFPTop View
Table 4-1 Pin Functions—Initialization, Clock, and Diagnostics
PINTYPEDESCRIPTION
NO.NAME
6WD1IWatchdog interrupt channel 1
7WD2IWatchdog interrupt channel 2
8PARK_ZODMD mirror parking signal (active low)
9RESET_ZOReset output to the DLPC23xS-Q1. TPS99000S-Q1 controlled.
10INT_ZOInterrupt output signal to DLPC23xS-Q1 (open drain). Recommended to pull up to the DLPC23xS-Q1 3.3V rail controlled by the TPS99000S-Q1's ENB_3P3V signal.
11PROJ_ONIInput signal to enable/disable the IC and DLP projector
16SEQ_STARTIPWM shadow latch control; indicates a start of sequence
17SEQ_CLKISequencer clock
40DMUX0ODigital test point output
41DMUX1ODigital test point output
57AMUX1OAnalog test mux output 1
61AMUX0OAnalog test mux output 0
Table 4-2 Pin Functions—Power and Ground
PINTYPEDESCRIPTION
NO.NAME
13, 35VSS_IOGNDGround connection for digital IO interface
14, 36VDD_IOPOWER3.3V power input for IO rail supply
24DVSSGNDDigital core ground return
25, 60, 75, 99PBKGGNDSubstrate tie and ESD ground return
26DVDDPOWER3.3V power input for digital core supply
42DRVR_PWRPOWER6V or 3.3V power input for FET driver power. Supply for S_EN1, S_EN2, R_EN, G_EN, and B_EN outputs
48VSS_DRVRGNDGround connection for FET driver power
49DMD_VOFFSETPOWERVOFFSET output rail. Connect a 1μF ceramic capacitor to ground
50DMD_VBIASPOWERVBIAS output rail. Connect a 0.47μF ceramic capacitor to ground
51DMD_VRESETPOWERVRESET output rail. Connect a 1μF ceramic capacitor to ground. Connect to DRST_HS_IND through external diode. Connect anode of diode to DMD_VRESET.
53DRST_PGNDGNDPower ground for DMD power supply. Connect to ground plane
55VIN_DRSTPOWER6V input for DMD power supply
56VSS_DRSTGNDGround supply for DMD power supply
59AVDDPOWER3.3V power supply input for analog circuit
63VLDOT_M8POWERDedicated TIA interface –8V LDO output
64VLDOT_5VPOWERFilter cap interface for 5V TIA LDO
65VIN_LDOT_5VPOWER6V power input for 5V TIA LDO
66GND_LDOGNDPower ground return for LDO
67VIN_LDOT_3P3VPOWER6V power input for 3.3V TIA LDO
68VLDOT_3P3VPOWERFilter cap interface for 3.3V TIA LDO
71VSS_TIA2GNDTIA2 Dedicated Ground
72VSS_TIA1GNDTIA1 dedicated ground
78, 100AVSSGNDAnalog ground
79VIN_LDOA_3P3POWER6V power input for dedicated ADC interface 3.3V LDO supply
80VLDOA_3P3POWERDedicated ADC interface 3.3V LDO filter cap output
81, 84, 87, 89, 91VSSL_ADCGNDExternal ADC channel bondwire and lead frame isolation ground
95ADC_VREFPOWERADC reference voltage output
Table 4-3 Pin Functions—Power Supply Management
PINTYPEDESCRIPTION
NO.NAME
1ENB_1P1VOExternal 1.1V buck enable. 3.3V output
2ENB_1P8VOExternal 1.8V buck enable. 3.3V output
3ENB_3P3VOExternal 3.3V buck enable. 3.3V output
52DRST_LS_INDANAConnection for the DMD power supply inductor (10μH). Connect a 330pF, 50V capacitor to ground. X7R recommended
54DRST_HS_INDANAConnection for the DMD power supply inductor (10μH)
58VMAINIMain intermediate voltage monitor input. Use an external resistor divider to set voltage input for brownout monitoring.
62VIN_LDOT_M8ODedicated TIA interface –8V LDO external regulation FET drive signal
96V3P3VIExternal 3.3V buck voltage monitor input
97V1P8VIExternal 1.8V buck voltage monitor input
98V1P1VIExternal 1.1V buck voltage monitor input
Table 4-4 Pin Functions—Illumination Control
PINTYPEDESCRIPTION
NO.NAME
12COMPOUTOPhotodiode (PD) interface high-speed comparator output
15SYNCOExternal LED buck driver sync strobe output
18D_ENILED interface; buck high-side FET drive enable
19S_ENILED bypass shunt strobe input
20LED_SEL_0ILED enable strobe 0 input
21LED_SEL_1ILED enable strobe 1 input
22LED_SEL_2ILED enable strobe 2 input
23LED_SEL_3ILED enable strobe 3 input
37EXT_SMPLIReserved. Connect to ground
38DRV_ENODrive enable for LM3409
39CMODEOCapacitor selection output (allows for a smaller capacitance to be used in CM mode for less overshoot or undershoot). Open drain.
43S_EN1OLow resistance shunt NFET drive enable [high means shunt active]
44S_EN2OHigh resistance shunt NFET drive enable [high means shunt active]
45R_ENORed channel select. Drive for low side NFET.
46G_ENOGreen channel select. Drive for low side NFET.
47B_ENOBlue channel select. Drive for low side NFET.
69TIA_PD2_FILTOTIA2 external filter cap - low bandwidth sampling
70TIA_PD2ITIA2 photodiode cathode driver
73TIA_PD1ITIA1 photodiode cathode driver
74TIA_PD1_FILTOTIA1 external filter cap - low bandwidth sampling
76R_IADJANAExternal resistance for IADJ voltage to current transformation
77IADJANACurrent output used to adjust external LED controller drive current set point
Table 4-5 Pin Functions—Serial Peripheral Interfaces
PINTYPEDESCRIPTION
NO.NAME
27SPI1_CLKISPI control interface (DLPC23xS-Q1 primary, TPS99000S-Q1 secondary), clock input
28SPI1_SS_ZISPI control interface (DLPC23xS-Q1 primary, TPS99000S-Q1 secondary), chip select (active low)
29SPI1_DOUTOSPI control interface (DLPC23xS-Q1 primary, TPS99000S-Q1 secondary), transmit data output
30SPI1_DINISPI control interface (DLPC23xS-Q1 primary, TPS99000S-Q1 secondary), receive data input
31SPI2_DINISPI diagnostic port (secondary), receive data input. For read-only monitoring
32SPI2_DOUTOSPI diagnostic port (secondary), transmit data output. For read-only monitoring
33SPI2_SS_ZISPI diagnostic port (secondary), chip select (active low). For read-only monitoring
34SPI2_CLKISPI diagnostic port (secondary), clock input. For read-only monitoring
Table 4-6 Pin Functions—Analog to Digital Converter
PINTYPEDESCRIPTION
NO.NAME
4ADC_MISOOADC 2-wire interface - data outputDLPC23xS-Q1 primary, TPS99000S-Q1 secondary.
5ADC_MOSIIADC 2-wire interface - data inputDLPC23xS-Q1 primary, TPS99000S-Q1 secondary.
82LS_SENSE_NILow side current sense ADC negative input, see Table 6-2
83LS_SENSE_PILow side current sense ADC positive input, see Table 6-2
85ADC_IN1IExternal ADC channel 1, see Table 6-2
86ADC_IN2IExternal ADC channel 2, see Table 6-2
88ADC_IN3IExternal ADC channel 3, see Table 6-2
90ADC_IN4IExternal ADC channel 4, see Table 6-2
92ADC_IN5IExternal ADC channel 5, see Table 6-2
93ADC_IN6IExternal ADC channel 6, see Table 6-2
94ADC_IN7IExternal ADC channel 7, see Table 6-2