SLVSG40 june   2023 TPSI2072-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
    1. 5.1 Pin Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Avalanche Robustness
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Dielectric Withstand Testing (HiPot)
      2. 9.2.2 Design Requirements
      3. 9.2.3 Design Procedure - Chassis Ground Reference
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.10 Switching Characteristics

Unless otherwise noted, all minimum/maximum specifications are over recommended operating conditions. All typical values are measured at TA = 25°C, VVDD = 5 V, VEN1,EN2 = 5 V.
MODE PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Switching Characteristics
EN switching tPD_ON Input HI to Output voltage falling propagation delay VIN = 600 V RL = 1 MΩ 300 µs
tF Output fall time 20 100
tON Input HI to Output LO delay 400
tPD_OFF Input LO to Output voltage rising propagation delay 200
tR Output rise time 600
tOFF Input LO to Output HI delay 700
EN and VDD switching tPD_ON Input HI to Output voltage falling propagation delay VIN = 600 V RL = 1 MΩ 400 µs
tF Output fall time 20 100
tON Input HI to Output LO delay 500
tPD_OFF Input LO to Output voltage rising propagation delay 200
tR Output rise time 600
tOFF Input LO to Output HI delay 700