SLVSFJ7D november   2021  – august 2023 TPSI3050-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Insulation Characteristic Curves
    12. 6.12 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Transmission of the Enable State
      2. 8.3.2 Power Transmission
      3. 8.3.3 Gate Driver
      4. 8.3.4 Modes Overview
      5. 8.3.5 Three-Wire Mode
      6. 8.3.6 Two-Wire Mode
      7. 8.3.7 VDDP, VDDH, and VDDM Undervoltage Lockout (UVLO)
      8. 8.3.8 Power Supply and EN Sequencing
      9. 8.3.9 Thermal Shutdown
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Two-Wire or Three-Wire Mode Selection
        2. 9.2.2.2 Standard Enable, One-Shot Enable
        3. 9.2.2.3 CDIV1, CDIV2 Capacitance
        4. 9.2.2.4 RPXFR Selection
        5. 9.2.2.5 CVDDP Capacitance
        6. 9.2.2.6 Gate Driver Output Resistor
        7. 9.2.2.7 Start-up Time and Recovery Time
        8. 9.2.2.8 Supplying Auxiliary Current, IAUX From VDDM
        9. 9.2.2.9 VDDM Ripple Voltage
      3. 9.2.3 Application Curves
      4. 9.2.4 Insulation Lifetime
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Related Links
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.8 Power Supply and EN Sequencing

During power up, the device will automatically determine if two-wire or three-wire mode is to be entered. Once two-wire or three-wire mode is determined, the mode is maintained until another power cycle is performed. Therefore, it is important to understand different scenarios that may affect the device operation.

In two-wire mode, the device is supplied power from a single external voltage source via EN, which charges the CVDDP capacitance on VDDP. The voltage supply is required to meet the power supply needs at the selected PXFR setting, as well as, meet the recommended minimum ramp time, |ΔVEN/Δt|. To ensure two-wire mode is entered properly, VEN must reach VIH_EN prior to VVDDP reaching VVDDP_UV_R. This is summarized in Figure 8-6. Similarly, it is recommend that VEN meet the minimum recommended ramp down time to VIL_EN. Too slow a ramp down time may cause insufficient power to be transferred while slowly transitioning between VIH_EN and VIL_EN leading to intermittent de-assertions and assertions of VDRV. This may continue until the power transfer reduces sufficiently to maintain VDRV low.

GUID-20221027-SS0I-0FHF-0KP5-LWMC4DV9ML6P-low.svg Figure 8-6 Two-wire Mode Entry

In most three-wire mode applications, EN and VDDP are supplied by the same voltage rail and source. It is recommended that VEN remain below VIL_EN until VVDDP reaches VVDDP_UV_R. It is also possible in some applications to connect EN directly to the VDDP supply. These two scenarios are shown in Figure 8-7.

GUID-20221027-SS0I-2PZ3-JS5K-ZHFXQPWXZMCX-low.svg Figure 8-7 Three-wire Mode Power Sequences

In three-wire mode applications with separate voltage sources supplying EN and VDDP, it is recommended that VEN remain below VIL_EN until VVDDP reaches VVDDP_UV_R. If VEN reaches VIH_EN prior to VVDDP reaching VVDDP_UV_R, current from the supply that sources EN will attempt to power VDDP. Depending on the other supply's impedance residing on VDDP and the amount of power available from the EN pin, VVDDP may begin to rise and eventually exceed VVDDP_UV_R. At that point, the device will begin to transfer power to the secondary and start charging the VDDM and VDDH rails. If VDDP remains above VVDDP_UV_R, the device will continue to transfer power to the secondary eventually charging the VDDM and VDDH rails and VDRV may assert high.