SLVSFJ7D november   2021  – august 2023 TPSI3050-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Insulation Characteristic Curves
    12. 6.12 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Transmission of the Enable State
      2. 8.3.2 Power Transmission
      3. 8.3.3 Gate Driver
      4. 8.3.4 Modes Overview
      5. 8.3.5 Three-Wire Mode
      6. 8.3.6 Two-Wire Mode
      7. 8.3.7 VDDP, VDDH, and VDDM Undervoltage Lockout (UVLO)
      8. 8.3.8 Power Supply and EN Sequencing
      9. 8.3.9 Thermal Shutdown
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Two-Wire or Three-Wire Mode Selection
        2. 9.2.2.2 Standard Enable, One-Shot Enable
        3. 9.2.2.3 CDIV1, CDIV2 Capacitance
        4. 9.2.2.4 RPXFR Selection
        5. 9.2.2.5 CVDDP Capacitance
        6. 9.2.2.6 Gate Driver Output Resistor
        7. 9.2.2.7 Start-up Time and Recovery Time
        8. 9.2.2.8 Supplying Auxiliary Current, IAUX From VDDM
        9. 9.2.2.9 VDDM Ripple Voltage
      3. 9.2.3 Application Curves
      4. 9.2.4 Insulation Lifetime
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Related Links
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Description

The TPSI3050-Q1 is a fully integrated, isolated switch driver, which when combined with an external power switch, forms a complete isolated solid state relay (SSR). With a nominal gate drive voltage of 10 V with 1.5/3.0-A peak source and sink current, a large variety of external power switches can be chosen to meet a wide range of applications. The TPSI3050-Q1 generates its own secondary bias supply from the power received from its primary side, so no isolated secondary supply bias is required. Additionally, the TPSI3050-Q1 can optionally supply power to external supporting circuitry for various application needs.

The TPSI3050-Q1 supports two modes of operation based on the number of input pins required. In two-wire mode, typically found in driving mechanical relays, controlling the switch requires only two pins and supports a wide voltage range of operation of 6.5 V to 48 V. In three-wire mode, the primary supply of 3 V to 5.5 V is supplied externally, and the switch is controlled through a separate enable. Available in three-wire mode only, the TPSI3050S-Q1 features a one-shot enable for the switch control. This feature is useful for driving SCRs that typically require only one pulse of current to trigger.

The secondary side provides a regulated, floating supply rail of 10 V for driving a large variety of power switches with no need for a secondary bias supply. The application can drive single power switches for DC applications or dual back-to-back power switches for AC applications, as well as various types of SCR. The TPSI3050-Q1 integrated isolation protection is extremely robust with much higher reliability, lower power consumption, and increased temperature ranges than traditional mechanical relays and optocouplers.

The power transfer of the TPSI3050-Q1 can be adjusted by selecting one of seven power level settings using an external resistor from the PXFR pin to VSSP. This action allows for tradeoffs in power dissipation versus power provided on the secondary depending on the needs of the application.

Package Information
PART NUMBERPACKAGE(1)BODY SIZE (NOM)
TPSI3050-Q1 SOIC 8-pin (DWZ) 7.50 mm × 5.85 mm
TPSI3050S-Q1
(1) For all available packages, see the orderable addendum at the end of the data sheet.
GUID-20201201-CA0I-MVGX-30JK-TVVQGXJQ26T1-low.svg TPSI3050-Q1 Simplified Schematic