SLVSFJ7D november   2021  – august 2023 TPSI3050-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Insulation Characteristic Curves
    12. 6.12 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Transmission of the Enable State
      2. 8.3.2 Power Transmission
      3. 8.3.3 Gate Driver
      4. 8.3.4 Modes Overview
      5. 8.3.5 Three-Wire Mode
      6. 8.3.6 Two-Wire Mode
      7. 8.3.7 VDDP, VDDH, and VDDM Undervoltage Lockout (UVLO)
      8. 8.3.8 Power Supply and EN Sequencing
      9. 8.3.9 Thermal Shutdown
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Two-Wire or Three-Wire Mode Selection
        2. 9.2.2.2 Standard Enable, One-Shot Enable
        3. 9.2.2.3 CDIV1, CDIV2 Capacitance
        4. 9.2.2.4 RPXFR Selection
        5. 9.2.2.5 CVDDP Capacitance
        6. 9.2.2.6 Gate Driver Output Resistor
        7. 9.2.2.7 Start-up Time and Recovery Time
        8. 9.2.2.8 Supplying Auxiliary Current, IAUX From VDDM
        9. 9.2.2.9 VDDM Ripple Voltage
      3. 9.2.3 Application Curves
      4. 9.2.4 Insulation Lifetime
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Related Links
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.9 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted). Typicals at TA = 25℃. CVDDP = 220 nF, CDIV1 = CDIV2 = 3.3 nF, CVDRV = 100 pF, RPXFR = 7.32 kΩ ± 1% 
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
COMMON
VVDDP_UV_R VDDP undervoltage threshold rising VDDP rising 2.50 2.70 2.90 V
VVDDP_UV_F VDDP undervoltage threshold falling VDDP falling 2.35 2.55 2.75 V
VVDDP_UV_HYS VDDP undervoltage threshold hysterisis 75 mV
TSD Temperature shutdown 173 ℃
TSDH Temperature shutdown hysteresis 32 ℃
VVDDH_UV_R VDDH undervoltage threshold rising VDDH rising. 8.3 8.6 9.0 V
VVDDH_UV_F VDDH undervoltage threshold falling
TPSI3050-Q1 only.		 VDDH falling. 6.3 6.6 6.9 V
VVDDH_UV_F VDDH undervoltage threshold falling
TPSI3050S-Q1 only. One-shot enable mode only available in three-wire operation.		 VDDH falling. 7.2 7.5 7.8 V
VVDDH_UV_HYS VDDH undervoltage threshold hysterisis
TPSI3050-Q1 only.		 2 V
VVDDH_UV_HYS VDDH undervoltage threshold hysterisis
TPSI3050S-Q1 only.		 1.1 V
IQ_VDDH Internal quiescent current of VDDH supply. 36 µA
RDSON_VDRV Driver on resistance in low state Force VVDDH = 10 V,
sink IVDRV = 50 mA.		 1.7 Ω
Driver on resistance in high state Force VVDDH = 10 V,
source IVDRV = 50 mA.		 2.5 Ω
IVDRV_PEAK VDRV peak output current during rise VVDDH in steady state,
transition EN from low to high,
measure peak current.
 1.5 A
VDRV peak output current during fall VVDDH in steady state,
transition EN from high to low,
measure peak current.
 3 A
CMTI Common-mode transient immunity |VCM| = 1000 V 100 V/ns
TWO-WIRE MODE
VIH_EN Minimum voltage on EN to be detected as a valid logic high 6.5 V
VIL_EN Maximum voltage on EN to be detected as a valid logic low 2.0 V
IEN_START Enable current at startup EN = 0 V → 6.5 V 27 mA
IEN Enable current steady state EN = 6.5 V,
RPXFR = 7.32 kΩ,
RPXFR ≥100 kΩ or RPXFR ≤1 kΩ,
VVDDH in steady state.		 1.9 mA
EN = 6.5 V,
RPXFR = 20 kΩ,
VVDDH in steady state.		 6.8 mA
VVDDP_RIPPLE VDDP output voltage ripple EN = 6.5 V, VVDDH in steady state. 600 mV
VVDDH VDDH output voltage EN = 6.5 V,
VVDDH in steady state.		 9.4 10.2 11 V
VVDRV_H VDRV output voltage driven high EN = 6.5 V,
VVDDH in steady state,
no DC loading.		 9.4 10.2 11 V
VVDRV_L VDRV output voltage driven low EN = 6.5 V → 0 V,
VVDDH in steady state,
sink 10 mA load.		 0.1 V
VVDDM_IAUX Average VDDM voltage when sourcing external current EN = 6.5 V, steady state.
RPXFR = 7.32 kΩ,
RPXFR ≥ 100 kΩ or RPXFR ≤ 1 kΩ,
CDIV1 = CDIV2 = 220 nF,

source 0.4 mA from VDDM,
measure VDDM voltage.		 4.6 5.5 V
EN = 6.5 V, steady state.
RPXFR = 20 kΩ,
CDIV1 = CDIV2 = 220 nF,

source 1.7 mA from VDDM,
measure VDDM voltage.		 4.6 5.5 V
THREE-WIRE MODE
VIH_EN Minimum voltage on EN to be detected as a valid logic high.  VIH(min) = 0.7 x VVDDP
 		 VVDDP = 3 V 2.1 V
VVDDP = 5.5 V 3.85 V
VIL_EN Maximum voltage on EN to be detected as a valid logic low VVDDP = 3 V 0.9 V
VVDDP = 5.5 V 1.65 V
IVDDP VDDP average current in steady state EN = 3.3 V,
VVDDP = 3.3 V,
RPXFR = 7.32 kΩ,
RPXFR ≥ 100 kΩ or RPXFR ≤ 1 kΩ,
VVDDH in steady state,
measure IVDDP.		 3.1 mA
EN = 3.3 V,
VVDDP = 3.3 V,
RPXFR = 20 kΩ
VVDDH in steady state,
measure IVDDP.		 26
EN = 5 V,
VVDDP = 5 V,
RPXFR = 7.32 kΩ,
RPXFR ≥ 100 kΩ or RPXFR ≤ 1 kΩ,
VVDDH in steady state,
measure IVDDP.		 4.8 mA
EN = 5 V,
VVDDP = 5 V,
RPXFR = 20 kΩ,
VVDDH in steady state,
measure IVDDP.		 37 mA
VVDDM_IAUX Average VDDM voltage when sourcing external current VVDDP = 3.3 V, EN = 0 V, steady state,
RPXFR = 7.32 kΩ,
CDIV1 = CDIV2 = 220 nF,

source 0.4 mA from VDDM,
measure VVDDM.		 4.6 5.5 V
VVDDP = 5.0 V, EN = 0 V, steady state,
RPXFR = 7.32 kΩ,
CDIV1 = CDIV2 = 220 nF,

source 1.0 mA from VDDM,
measure VVDDM.		 4.6 5.5 V
VVDDP = 3.3 V, EN = 0 V, steady state,
RPXFR =20 kΩ,
CDIV1 = CDIV2 = 220 nF,

source 5.5 mA from VDDM,
measure VVDDM.		 4.6 5.5 V
VVDDP = 5.0 V, EN = 0 V, steady state,
RPXFR = 20 kΩ,
CDIV1 = CDIV2 = 220 nF,

source 10 mA from VDDM,
measure VVDDM.		 4.6 5.5 V
VVDDH VDDH output voltage VVDDP = 3.0 V,
EN = 3.0 V,
VVDDH in steady state.		 9.4 10.2 11 V
VVDRV_H VDRV output voltage driven high VVDDP = 3.0 V,
EN = 3.0 V,
VVDDH in steady state, no DC loading.		 9.4 10.2 11 V
VVDRV_L VDRV output voltage driven low VVDDP = 3.0 V,
EN = 0 V,
VVDDH in steady state,
VDRV sinking 10 mA.		 0.1 V