SLVSFY5C april   2022  – august 2023 TPSI3052-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Insulation Characteristic Curves
    12. 6.12 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Transmission of the Enable State
      2. 8.3.2 Power Transmission
      3. 8.3.3 Gate Driver
      4. 8.3.4 Modes Overview
      5. 8.3.5 Three-Wire Mode
      6. 8.3.6 Two-Wire Mode
      7. 8.3.7 VDDP, VDDH, and VDDM Undervoltage Lockout (UVLO)
      8. 8.3.8 Power Supply and EN Sequencing
      9. 8.3.9 Thermal Shutdown
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Two-Wire or Three-Wire Mode Selection
        2. 9.2.2.2 Standard Enable, One-Shot Enable
        3. 9.2.2.3 CDIV1, CDIV2 Capacitance
        4. 9.2.2.4 RPXFR Selection
        5. 9.2.2.5 CVDDP Capacitance
        6. 9.2.2.6 Gate Driver Output Resistor
        7. 9.2.2.7 Start-up Time and Recovery Time
        8. 9.2.2.8 Supplying Auxiliary Current, IAUX From VDDM
        9. 9.2.2.9 VDDM Ripple Voltage
      3. 9.2.3 Application Curves
      4. 9.2.4 Insulation Lifetime
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Related Links
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.12 Typical Characteristics

GUID-20220425-SS0I-GNCN-FS4N-DP6F7HDW5QR6-low.svg
Three-wire mode VDDP = 5.0 V RPXFR = 7.32 kΩ
CDIV1 = 5.1 nF CVDRV = 100 pF TA = 25°C
CDIV2 =15 nF CVDDP = 1 μF IAUX = 0 mA
Figure 6-4 tLH_VDRV, Three-Wire Mode
GUID-20221201-SS0I-WDDJ-PD8G-7MW9KRZB2C02-low.svg
Three-wire mode VDDP = 3.3 V RPXFR = 7.32 kΩ
CDIV1 = 2.2 μF CDIV2 = 2.2 μF
Figure 6-6 tLH_VDRV versus CVDRV
GUID-20221128-SS0I-6M8N-MZH1-LKF5JV28BRZF-low.svg
Two-wire mode EN = 12 V RPXFR = 7.32 kΩ
CDIV1 = 33 nF CVDRV = 100 pF TA = 25°C
CDIV2 =100 nF CVDDP = 220 nF IAUX = 0 mA
Figure 6-8 tLH_VDRV, Two-Wire Mode
GUID-20221202-SS0I-VFDX-KXXL-DLZN52CDQT4H-low.svg
tSTART represents the time from VDDP rising to VDDM and VDDH fully discharged rails reaching > 95% of their final levels.
Three-wire mode VDDP = 5.0 V TA = 25°C
IAUX = 0 mA
Figure 6-10 tSTART versus CDIV1, CDIV2
GUID-20221202-SS0I-NNX7-BWFS-LV4JR55GD1XM-low.svg
Three-wire mode VDDP = 5.0 V TA = 25°C
IAUX = 0 mA
Figure 6-12 Max. fEN versus QLOAD = 10 nC to 100 nC
GUID-20221201-SS0I-JZQS-LJNX-T9CG6TVGWWJQ-low.svg
Three-wire mode RPXFR = 20 kΩ TA = 25°C
CDIV1 = 150 nF CDIV2 = 470 nF CVDDP = 1 μF
Figure 6-14 VVDDM versus IAUX
GUID-20220425-SS0I-C9XP-45HP-1NMGKRDVN94B-low.svg
Three-wire mode VDDP = 5.0 V RPXFR = 7.32 kΩ
CDIV1 = 5.1 nF CVDRV = 100 pF TA = 25°C
CDIV2 =15 nF CVDDP = 1 μF IAUX = 0 mA
Figure 6-5 tHL_VDRV, Three-Wire Mode
GUID-20221201-SS0I-NFS8-M8MR-GNFDXSTD6MRM-low.svg
Three-wire mode VDDP = 3.3 V RPXFR = 7.32 kΩ
CDIV1 = 2.2 μF CDIV2 = 2.2 μF
Figure 6-7 tHL_VDRV versus CVDRV
GUID-20221128-SS0I-FNMS-NJ9S-SCSF37GMVKKQ-low.svg
Two-wire mode EN = 12 V RPXFR = 7.32 kΩ
CDIV1 = 33 nF CVDRV = 100 pF TA = 25°C
CDIV2 =100 nF CVDDP = 220 nF IAUX = 0 mA
Figure 6-9 tHL_VDRV, Two-Wire Mode
GUID-20221202-SS0I-N4CW-TGSM-MJPZ89M9T1FH-low.svg
tSTART represents the time from VDDP rising to VDDM and VDDH fully discharged rails reaching > 95% of their final levels.
Three-wire mode VDDP = 3.3 V TA = 25°C
IAUX = 0 mA
Figure 6-11 tSTART versus CDIV1, CDIV2
GUID-20221202-SS0I-6TZC-8XJC-62NNQ5KFBHWL-low.svg
Three-wire mode VDDP = 5.0 V TA = 25°C
IAUX = 0 mA
Figure 6-13 Max. fEN versus QLOAD = 100 nC to 1000 nC
GUID-20221201-SS0I-T9K3-9TZN-R1BG5NHC9SX2-low.svg
Three-wire mode RPXFR = 11 kΩ TA = 25°C
CDIV1 = 150 nF CDIV2 = 470 nF CVDDP = 1 μF
Figure 6-15 VVDDM versus IAUX