SLVSGS3B april   2022  – august 2023 TPSI3052

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Insulation Characteristic Curves
    12. 6.12 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Transmission of the Enable State
      2. 8.3.2 Power Transmission
      3. 8.3.3 Gate Driver
      4. 8.3.4 Modes Overview
      5. 8.3.5 Three-Wire Mode
      6. 8.3.6 Two-Wire Mode
      7. 8.3.7 VDDP, VDDH, and VDDM Undervoltage Lockout (UVLO)
      8. 8.3.8 Power Supply and EN Sequencing
      9. 8.3.9 Thermal Shutdown
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Two-Wire or Three-Wire Mode Selection
        2. 9.2.2.2 Standard Enable, One-Shot Enable
        3. 9.2.2.3 CDIV1, CDIV2 Capacitance
        4. 9.2.2.4 RPXFR Selection
        5. 9.2.2.5 CVDDP Capacitance
        6. 9.2.2.6 Gate Driver Output Resistor
        7. 9.2.2.7 Start-up Time and Recovery Time
        8. 9.2.2.8 Supplying Auxiliary Current, IAUX From VDDM
        9. 9.2.2.9 VDDM Ripple Voltage
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Related Links
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.10 Switching Characteristics

over operating free-air temperature range (unless otherwise noted). Typicals at TA = 25℃. CVDDP = 220 nF (two-wire mode), CVDDP = 1 µF (three-wire mode) , CDIV1 = 5.1 nF, CDIV2 = 15 nF,  CVDRV = 100 pF, RPXFR = 7.32 kΩ ±1% 
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TWO-WIRE MODE
tLO_EN Low time of EN. 5 µs
tLH_VDDH Propagation delay time from EN rising to VDDH at 50% level. EN = 0 V → 6.5 V,
VVDDH = 7.5 V.		 165 µs
tLH_VDRV Propagation delay time from EN rising to VDRV at 90% level. EN = 0 V → 6.5 V,
VVDRV = 13.5 V.		 185 µs
tHL_VDRV Propagation delay time from EN falling to VDRV at 10% level. EN = 6.5 V → 0 V,
VVDRV = 1.5 V.		 2.4 3 µs
tR_VDRV VDRV rise time from EN rising to VDRV from 15% to 85% level. EN = 0 V → 6.5 V,
VVDRV = 2.25 V to 12.75 V.		 6 ns
tF_VDRV VDRV fall time from EN falling to VDRV from 85% to 15% level. EN = 6.5 V → 0 V,
VVDRV = 12.75 V to 2.25 V.		 5 ns
THREE-WIRE MODE
tLO_EN Low time of EN. VVDDP = 3.3 V, VVDDH = steady state. 5 µs
tHI_EN High time of EN. VVDDP = 3.3 V, VVDDH = steady state. 5 µs
tHI_VDRV High time of VDRV in one-shot enable mode.
TPSI3052S only.
One-shot enable only available in three-wire mode.		 VVDDP = 3.3 V, steady state. 2.5 µs
tLH_VDDH Propagation delay time from VDDP rising to VDDH at 50% level. EN = 0 V,
VVDDP =  0 V → 3.3 V at 1 V/µs,
VVDDH = 7.5 V.
CDIV1 = 3.3 nF, CDIV2 = 220 nF.		 85 µs
tLH_VDRV Propagation delay time from EN rising to VDRV at 90% level VVDDP = 3.3 V,
VVDDH steady state,
EN = 0 V → 3.3 V,
VVDRV = 13.5 V.		 3 4.5 µs
tHL_VDRV Propagation delay time from EN falling to VDRV at 10% level VVDDP = 3.3 V,
VVDDH steady state,
EN = 3.3 V → 0 V,
VVDRV = 1.5 V.		 2.5 3 µs
tHL_VDRV_PD Propagation delay time from VDDP falling to VDRV at 10% level. Timeout mechanism due to loss of power on primary supply. EN = 3.3 V,
VVDDP =  3.3 V → 0 V at -1 V/µs,
VVDRV = 1.5 V.		 300 µs
tR_VDRV VDRV rise time from EN rising to VDRV from 15% to 85% level VVDDP = 3.3 V,
VVDDH steady state,
EN =  0 V → 3.3 V,
VVDRV = 2.25 V to 12.75 V.		 6 ns
tF_VDRV VDRV fall time from EN falling to VDRV from 85% to 15% level VVDDP = 3.3 V,
VVDDH steady state,
EN =  3.3 V → 0 V,
VVDRV = 12.75 V to 2.25 V.		 5 ns