SLVSG43A December   2023  – November 2024 TPSI3100-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Insulation Characteristic Curves
    12. 6.12 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Transmission of the Enable State
      2. 8.3.2 Power Transmission
      3. 8.3.3 Gate Driver
      4. 8.3.4 Chip Enable (CE)
      5. 8.3.5 Comparators
        1. 8.3.5.1 Fault Comparator
        2. 8.3.5.2 Alarm Comparator
        3. 8.3.5.3 Comparator De-glitch
      6. 8.3.6 VDDP, VDDH, and VDDM Undervoltage Lockout (UVLO)
      7. 8.3.7 Keep-Off Circuitry
      8. 8.3.8 Thermal Shutdown
    4. 8.4 Device Operation
    5. 8.5 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 CDIV1, CDIV2 Capacitance
        2. 9.2.2.2 Start-up Time and Recovery Time
        3. 9.2.2.3 RSHUNT, R1, and R2 Selection
        4. 9.2.2.4 Overcurrent Fault Error
        5. 9.2.2.5 Overcurrent Alarm Error
        6. 9.2.2.6 VDDP Capacitance, CVDDP
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DVX|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Description

The TPSI3100-Q1 is a fully integrated isolated switch driver, which when combined with an external power switch, forms a complete isolated solid state relay solution. With a gate drive voltage of 17V with 1.5A and 2.5A peak source and sink current, a large availability of power switches can be used to meet many application needs. The TPSI3100-Q1 generates its own secondary bias supply from power received on its primary side, so no isolated secondary supply bias is required. The TPSI3100-Q1 provides additional power via the nominal 5V rail (VDDM) for use by auxiliary circuits to perform various function such as current and voltage monitoring or remote temperature detection. The TPSI3100-Q1 isolation is extremely robust with much higher reliability, lower power consumption, and increased temperature ranges than those found using traditional mechanical relays and optocouplers.

The TPSI3100-Q1 integrates a communication back-channel that transfers status information from the secondary side to the primary side via open-drain outputs, PGOOD (Power Good), FLT1 (Fault 1), and ALM1 (Alarm 1). Dual high-speed comparators with an integrated shared voltage reference are used to assert FLT1 and ALM1. When the comparator input, FLT1_CMP, exceeds the voltage reference, the driver is immediately asserted low and FLT1 is also driven low, indicating to the system that a fault has occurred. This is useful for disabling the external switch with low latency on critical events, such as overcurrent detection. When the comparator input, ALM1_CMP, exceeds the voltage reference, ALM1 signal is asserted low, but no action is taken by the driver. This may be useful as an alarm or warning indicator for overtemperature or overvoltage events.

The TPSI310xL-Q1 series offers a latch based fault indicator. When a fault is detected, the driver and the fault indicator are asserted low and remain latched, until EN is asserted low. The TPSI310x-Q1 series has a non-latched fault indicator. If the fault event is no longer present, FLT1 deasserts and the driver, after a specified recovery period, follows the state of the EN pin. If the fault event still remains, both the fault indicator and the driver remain asserted low.

Device Information
PART NUMBER REF(2) COMPARATORS(2) PACKAGE(1)
TPSI3100-Q1 0.31V 1 fault, 1 alarm DVX (SSOP, 16)
TPSI3100L-Q1 0.31V 1 latched fault,
1 alarm
(1) For all available packages, see the orderable addendum at the end of the data sheet.
(1) Product preview.
TPSI3100-Q1 TPSI3100-Q1 Simplified Schematic TPSI3100-Q1 Simplified Schematic