The TPSI310x-Q1 is a fully integrated, isolated switch driver with integrated bias, which when combined with an external power switch, forms a complete isolated solid state relay solution. With a nominal gate drive voltage of 17V with 1.5A and 3.0A peak source and sink current, a large variety of external power switches such as MOSFETs, IGBTs, or SCRs can be chosen to meet a wide range of applications. The TPSI310x-Q1 generates its own secondary bias supply from the power received from its primary side, so no isolated secondary supply bias is required.

The secondary side provides a regulated, floating supply rail of 17V for driving a large variety of power switches with no need for a secondary bias supply. The TPSI310x-Q1 can support driving single power switch, dual back-to-back, parallel power switches for a variety of AC or DC applications. The TPSI310x-Q1 integrated isolation protection is extremely robust with much higher reliability, lower power consumption, and increased temperature ranges than those found using traditional mechanical relays and optocouplers.

The TPSI310x-Q1 integrates a communication back-channel that transfers various status information from the secondary side to the primary side via open-drain outputs, PGOOD (Power Good), FLT1 (Fault 1), and ALM1 (Alarm 1). Two high-speed comparators with an integrated shared voltage reference are used to assert FLT1 and ALM1. When the comparator input, FLT1_CMP, exceeds the voltage reference, the driver is immediately asserted low and FLT1 on the primary side is driven low after some latency, indicating a fault has occurred. This is useful for directly disabling the external switch from the secondary on critical events with low latency, such as short circuit detection. When the comparator input, ALM1_CMP, exceeds the voltage reference, ALM1 signal is asserted low on the primary side, but no action is taken by the driver. This may be useful as an alarm or warning indicator.

The various devices offered in the family can be used in a broad range of applications, with just some examples shown here. Figure 9-1 shows a simplified schematic of a shunt based overcurrent protection for DC applications. As the voltage increases across R_SHUNT, an alarm event is triggered upon crossing the VREF threshold of the alarm comparator and ALM1 asserts low notifying the system of the event. As the voltage increases further, a fault event is triggered upon crossing the VREF threshold of the fault comparator, which immediately asserts VDRV low to protect the FET and the downstream load. FLT1 asserts low notifying the system of the event.

Figure 9-1 TPSI3100-Q1 overcurrent protection with fault and alarm indicators

Figure 9-2 shows a simplified schematic of a shunt based overcurrent protection using a current sense amplifier for DC applications. The current sense amplifier, with its low input offset, allows for using smaller value R_SHUNT values for lower power losses for larger current ranges. As the voltage increases across R_SHUNT, after being amplified by the current sense amplifier, an alarm event is triggered upon crossing the VREF threshold of the alarm comparator and ALM1 asserts low notifying the system of the event. As the voltage increases further, a fault event is triggered upon crossing the VREF threshold of the fault comparator, which immediately asserts VDRV low to protect the FET and the downstream load. FLT1 asserts low notifying the system of the event.

Figure 9-2 TPSI310x-Q1 overcurrent protection with current sense amplifier, fault and alarm indicators

Figure 9-3 shows a simplified schematic of a shunt based overcurrent protection for AC applications. As the positive AC voltage increases across R_SHUNT1, a fault event is triggered upon crossing the VREF threshold of the first fault comparator, which immediately asserts VDRV low to protect the back-to-back FETs and the downstream load. FLT1 asserts low notifying the system of the event. Similarly, as the negative AC voltage increases across R_SHUNT2, a fault event is triggered upon crossing the VREF threshold of the second fault comparator, which immediately asserts VDRV low. FLT2 asserts low notifying the system of the event.

Figure 9-3 TPSI3110-Q1 Bi-directional overcurrent protection with fault indicators

Figure 9-4 shows a simplified schematic of a shunt based overcurrent protection using dual current sense amplifiers for AC applications. In this topology, a single shunt resistor is used. The top current sense amplifier connects its IN+ and IN- pins across R_SHUNT, where the second current sense amplifier reverses its input connections. As the positive AC voltage increases across R_SHUNT, after being amplified by the top current sense amplifier, a fault event is triggered upon crossing the VREF threshold of the first fault comparator, which immediately asserts VDRV low to protect the back-to-back FETs and the downstream load. FLT1 asserts low notifying the system of the event. Similarly, as the negative AC voltage increases across R_SHUNT, a fault event is triggered upon crossing the VREF threshold of the second fault comparator, which immediately asserts VDRV low. FLT2 asserts low notifying the system of the event.

Figure 9-4 TPSI311x-Q1 Bi-directional overcurrent protection with current sense amplifiers, fault indicators

Figure 9-5 shows a simplified schematic of overcurrent protection using DESAT protection for DC applications. This method is commonly used with IGBT power transistors. When the IGBT is off, FLT1_CMP is driven low internally by the TPSI3133-Q1. When the driver is being enabled, the voltage on FLT1_CMP begins to rise. As the IGBT turns on, under normal load conditions, its V_CE drops quickly which causes the voltage on FLT1_CMP to remain below the fault comparator threshold. The time for when FLT1_CMP is released and V_CE has dropped enough to keep a false fault event from being detected, is known as the blanking time. Adjusting RESP value can help increase the required blanking time or some capacitance may be added to FLT1_CMP. If overcurrent conditions occur, V_CE begins to rise until the voltage on FLT1_CMP reaches the VREF threshold of the fault comparator. VDRV is asserted low to protect the IGBT and the downstream load. FLT1 asserts low notifying the system of the event.

Figure 9-5 TPSI3133-Q1 DESAT protection with fault indicator