SLVSG43A December   2023  – November 2024 TPSI3100-Q1

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Insulation Characteristic Curves
    12. 6.12 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Transmission of the Enable State
      2. 8.3.2 Power Transmission
      3. 8.3.3 Gate Driver
      4. 8.3.4 Chip Enable (CE)
      5. 8.3.5 Comparators
        1. 8.3.5.1 Fault Comparator
        2. 8.3.5.2 Alarm Comparator
        3. 8.3.5.3 Comparator De-glitch
      6. 8.3.6 VDDP, VDDH, and VDDM Undervoltage Lockout (UVLO)
      7. 8.3.7 Keep-Off Circuitry
      8. 8.3.8 Thermal Shutdown
    4. 8.4 Device Operation
    5. 8.5 Device Functional Modes
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 CDIV1, CDIV2 Capacitance
        2. 9.2.2.2 Start-up Time and Recovery Time
        3. 9.2.2.3 RSHUNT, R1, and R2 Selection
        4. 9.2.2.4 Overcurrent Fault Error
        5. 9.2.2.5 Overcurrent Alarm Error
        6. 9.2.2.6 VDDP Capacitance, CVDDP
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DVX|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Alarm Comparator

The TPSI310x-Q1 and TPSI3133-Q1 devices include one alarm comparator. The TPSI312x-Q1 devices include two alarm comparators. An alarm comparator differs from the fault comparator in that the output state of the comparator has no direct control of the VDRV output driver. The block diagram of the alarm comparator is shown in Figure 8-8.

TPSI3100-Q1 Alarm Comparator Block
                    Diagram Figure 8-8 Alarm Comparator Block Diagram

If the input voltage of the alarm comparator, ALM1_CMP, exceeds the internal reference voltage, VREF, the comparator output asserts high. The comparator output is filtered and is adjustable via an external 1% resistor, RRESP, connected from RESP to VSSS. The filtering of low-to-high transitions of the comparator output is adjustable by RRESP. High-to-low transitions of the comparator output are filtered at a fixed setting. The filter setting is shared by both the fault and alarm comparators and cannot be set independently. In addition, the alarm comparator is not latched.

Similar to the fault comparator, the alarm comparator output information is transferred to the primary side of the device via back-channel communication (BCC) over the isolation barrier. As shown in Figure 8-8, any low-to-high transition of the comparator output (alarm event) that passes through the filter is extended to make sure the event is captured by the sample logic. Any high-to-low transition of the comparator output (recovery event) that passes through the filter are not extended. A recovery event can be missed by the sample logic if the event does not last longer than the sample period. Therefore, priority is given to alarm events over recovery events. ALM1 open-drain output is asserted low upon the alarm event. If a recovery event occurs and is captured by the sample logic, ALM1 open-drain output is set to high-impedance.