SLVSG43A December   2023  – November 2024 TPSI3100-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Insulation Characteristic Curves
    12. 6.12 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Transmission of the Enable State
      2. 8.3.2 Power Transmission
      3. 8.3.3 Gate Driver
      4. 8.3.4 Chip Enable (CE)
      5. 8.3.5 Comparators
        1. 8.3.5.1 Fault Comparator
        2. 8.3.5.2 Alarm Comparator
        3. 8.3.5.3 Comparator De-glitch
      6. 8.3.6 VDDP, VDDH, and VDDM Undervoltage Lockout (UVLO)
      7. 8.3.7 Keep-Off Circuitry
      8. 8.3.8 Thermal Shutdown
    4. 8.4 Device Operation
    5. 8.5 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 CDIV1, CDIV2 Capacitance
        2. 9.2.2.2 Start-up Time and Recovery Time
        3. 9.2.2.3 RSHUNT, R1, and R2 Selection
        4. 9.2.2.4 Overcurrent Fault Error
        5. 9.2.2.5 Overcurrent Alarm Error
        6. 9.2.2.6 VDDP Capacitance, CVDDP
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DVX|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.6 VDDP, VDDH, and VDDM Undervoltage Lockout (UVLO)

The TPSI310x-Q1, TPSI311x-Q1, TPSI312x-Q1, and TPSI3133-Q1 family implements an internal UVLO protection feature for both input (VDDP) and output power supplies (VDDM and VDDH). The device remains disabled until VDDP exceeds its rising UVLO threshold. When the VDDP supply voltage falls below its falling threshold voltage, the device attempts to send data information to quickly assert VDRV low, regardless of the state of EN. This depends on the rate of VDDP loss. If VDDP collapses too fast to send the information, a timeout mechanism ensures VDRV is asserted low within tHL_VDRV_PD. A VDDP ULVO event causes PGOOD, FLT1, and ALM1 to assert low.

VDDH and VDDM UVLO circuits monitor the voltage on VDDH and VDDM, respectively. VDRV is only asserted high if both the VDDH and VDDM UVLO rising thresholds are surpassed. If either VDDH or VDDM fall below their respective UVLO falling thresholds, VDRV is immediately asserted low. The UVLO protection blocks feature hysteresis, which helps to improve immunity of VDRV to noise present on the VDDM and VDDH rails. During turn on and turn off, the driver sources and sinks a peak transient current, which can result in voltage drop of the VDDH and VDDM power supplies. The UVLO protection circuits ignores the associated noise during these normal switching transients.