SLVSG43A December   2023  – November 2024 TPSI3100-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Insulation Characteristic Curves
    12. 6.12 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Transmission of the Enable State
      2. 8.3.2 Power Transmission
      3. 8.3.3 Gate Driver
      4. 8.3.4 Chip Enable (CE)
      5. 8.3.5 Comparators
        1. 8.3.5.1 Fault Comparator
        2. 8.3.5.2 Alarm Comparator
        3. 8.3.5.3 Comparator De-glitch
      6. 8.3.6 VDDP, VDDH, and VDDM Undervoltage Lockout (UVLO)
      7. 8.3.7 Keep-Off Circuitry
      8. 8.3.8 Thermal Shutdown
    4. 8.4 Device Operation
    5. 8.5 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 CDIV1, CDIV2 Capacitance
        2. 9.2.2.2 Start-up Time and Recovery Time
        3. 9.2.2.3 RSHUNT, R1, and R2 Selection
        4. 9.2.2.4 Overcurrent Fault Error
        5. 9.2.2.5 Overcurrent Alarm Error
        6. 9.2.2.6 VDDP Capacitance, CVDDP
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DVX|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.12 Typical Characteristics

TPSI3100-Q1 tLH_VDRV
VDDP = 5.0V TA = 25°C
CDIV1 = 47nF CDIV2 = 220nF CVDRV = 1nF
Figure 6-3 tLH_VDRV
TPSI3100-Q1 tLH_VDRV versus CVDRV
VDDP = 5.0V
CDIV1 = 3.3μF CDIV2 = 10μF
Figure 6-5 tLH_VDRV versus CVDRV
TPSI3100-Q1 tLH_VDRV_CE
VDDP = 5.0V TA = 25°C RRESP = 100kΩ
CDIV1 = 47nF CDIV2 = 220nF CVDRV = 1nF
Figure 6-7 tLH_VDRV_CE
TPSI3100-Q1 tHL_VDRV_CE(zoomed out)
VDDP = 5.0V TA = 25°C RRESP = 100kΩ
CDIV1 = 47nF CDIV2 = 220nF CVDRV = 1nF
Figure 6-9 tHL_VDRV_CE(zoomed out)
TPSI3100-Q1 tPD_CMP_VDRV_DIS, tFLT_LATENCY
VDDP = 5.0V TA = 25°C RRESP = 100kΩ
CDIV1 = 47nF CDIV2 = 220nF CVDRV = 1nF
Figure 6-11 tPD_CMP_VDRV_DIS, tFLT_LATENCY
TPSI3100-Q1 tHL_VDRV
VDDP = 5.0V TA = 25°C
CDIV1 = 47nF CDIV2 = 220nF CVDRV = 1nF
Figure 6-4 tHL_VDRV
TPSI3100-Q1 tHL_VDRV versus CVDRV
VDDP = 5.0V
CDIV1 = 3.3μF CDIV2 = 10μF
Figure 6-6 tHL_VDRV versus CVDRV
TPSI3100-Q1 tHL_VDRV_CE(zoomed in)
VDDP = 5.0V TA = 25°C RRESP = 100kΩ
CDIV1 = 47nF CDIV2 = 220nF CVDRV = 1nF
Figure 6-8 tHL_VDRV_CE(zoomed in)
TPSI3100-Q1 VVDDM versus IAUX
VDDP = 5.0V CDIV1 = 47nF CDIV2 = 220nF
Figure 6-10 VVDDM versus IAUX
TPSI3100-Q1 tPD_CMP_VDRV_DIS, tFLT_LATENCY
VDDP = 5.0V TA = 25°C RRESP = 500kΩ
CDIV1 = 47nF CDIV2 = 220nF CVDRV = 1nF
Figure 6-12 tPD_CMP_VDRV_DIS, tFLT_LATENCY