SLVSG43A December   2023  – November 2024 TPSI3100-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Insulation Characteristic Curves
    12. 6.12 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Transmission of the Enable State
      2. 8.3.2 Power Transmission
      3. 8.3.3 Gate Driver
      4. 8.3.4 Chip Enable (CE)
      5. 8.3.5 Comparators
        1. 8.3.5.1 Fault Comparator
        2. 8.3.5.2 Alarm Comparator
        3. 8.3.5.3 Comparator De-glitch
      6. 8.3.6 VDDP, VDDH, and VDDM Undervoltage Lockout (UVLO)
      7. 8.3.7 Keep-Off Circuitry
      8. 8.3.8 Thermal Shutdown
    4. 8.4 Device Operation
    5. 8.5 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 CDIV1, CDIV2 Capacitance
        2. 9.2.2.2 Start-up Time and Recovery Time
        3. 9.2.2.3 RSHUNT, R1, and R2 Selection
        4. 9.2.2.4 Overcurrent Fault Error
        5. 9.2.2.5 Overcurrent Alarm Error
        6. 9.2.2.6 VDDP Capacitance, CVDDP
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DVX|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.3 Application Curves

TPSI3100-Q1 Overcurrent Protection Typical Timing and Behavior Figure 9-7 Overcurrent Protection Typical Timing and Behavior
  • At t0: VDRV is asserted high and the external FETs are supplying load current, ILOAD. ILOAD is in its normal operating range and is below the alarm level setting of 4A, nominal. ALM1_CMP and FLT1_CMP comparator input voltages are below the comparator threshold set by VREF of the TPSI3100-Q1 of 0.31V,nominal). ALM1 and FLT1 faults are asserted high pulled-up by external resistor pull-ups to VDDP.
  • At t1: ILOAD current increases and reaches the alarm level setting of 4A, nominal. ALM1_CMP comparator input voltage reaches its threshold of 0.31V and ALM1 asserts low within tALM_LATENCY. VDRV remains asserted high since the FLT1_CMP comparator input threshold has not been reached. FLT1 remains asserted high pulled-up by the external resistor pull-up to VDDP.
  • At t2: ILOAD current continues to increases and reaches the fault level setting of 8A, nominal. FLT1_CMP comparator input voltage reaches its threshold of 0.31V and VDRV is quickly asserted low to disable the external FETs. FLT1 asserts low within tFLT_LATENCY. ALM1 remains asserted low since the ALM1_CMP comparator input exceeds its threshold.
  • At t3: Since the FETs have been turned off, ILOAD, is removed. FLT1_CMP and ALM1_CMP comparator inputs drop below their thresholds, settling to VSSS. VDRV remains asserted low keeping the external FETs off for tREC_VDRV. FLT1 and ALM1 assert high within tFLT_LATENCY and tALM_LATENCY, respectively indicating to the system that fault and alarm conditions have been removed.
  • At t4: VDRV asserts high again since EN remains high, tREC_VDRV time has elapsed, and the fault condition is no longer present. The external FETs are enabled and supply ILOAD in its normal operating range.

Figure 9-8 shows a typical waveform capture. At time 0μs, a load current (ILOAD) pulse of over 5A is applied. Since this is above the alarm comparator threshold of 4.13A, ALM1 indicator is asserted low within tALM_LATENCY, in this case, near time 5μs. Approximately at time 15µs, a load current pulse of over 10A is applied. Since this is above the fault comparator threshold of 8.27A, VDRV is quickly asserted low to protect the power FET, and ILOAD drops to 0A. FLT1 is asserted low within tFLT_LATENCY, in this case, near time 30μs. Both the fault and alarm comparator thresholds are exceeded on the second load current pulse. After ILOAD falls below both the fault and alarm comparator thresholds, ALM1 and FLT1 assert high near time 55μs, indicating no alarm or fault is present. VDRV remains asserted low until tREC_VDRV time elapses, near time 180μs.

TPSI3100-Q1 Overcurrent Protection and VDRV Auto-recovery Figure 9-8 Overcurrent Protection and VDRV Auto-recovery