SLVSG43A December   2023  – November 2024 TPSI3100-Q1

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Insulation Characteristic Curves
    12. 6.12 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Transmission of the Enable State
      2. 8.3.2 Power Transmission
      3. 8.3.3 Gate Driver
      4. 8.3.4 Chip Enable (CE)
      5. 8.3.5 Comparators
        1. 8.3.5.1 Fault Comparator
        2. 8.3.5.2 Alarm Comparator
        3. 8.3.5.3 Comparator De-glitch
      6. 8.3.6 VDDP, VDDH, and VDDM Undervoltage Lockout (UVLO)
      7. 8.3.7 Keep-Off Circuitry
      8. 8.3.8 Thermal Shutdown
    4. 8.4 Device Operation
    5. 8.5 Device Functional Modes
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 CDIV1, CDIV2 Capacitance
        2. 9.2.2.2 Start-up Time and Recovery Time
        3. 9.2.2.3 RSHUNT, R1, and R2 Selection
        4. 9.2.2.4 Overcurrent Fault Error
        5. 9.2.2.5 Overcurrent Alarm Error
        6. 9.2.2.6 VDDP Capacitance, CVDDP
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DVX|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Pin Configuration and Functions

TPSI3100-Q1 TPSI310x-Q1 and TPSI310xL-Q1DVX Package, 16-Pin SSOP(Top View) Figure 5-1 TPSI310x-Q1 and TPSI310xL-Q1DVX Package, 16-Pin SSOP(Top View)
PIN I/O TYPE(1) DESCRIPTION
NO. NAME
1 EN I Active high driver enable. Internal 500kΩ pull-down to VSSP.
2 CE I Active high input. When asserted low, device is disabled. Tie to VDDP when not used. Internal 500kΩ pull-down to VSSP.
3 VSSP GND Ground supply for primary side. All VSSP pins must be connected to the primary side ground.
4 VDDP P Power supply for the primary side.
5 PGOOD O Power good indicator. Open-drain output. When being used, requires external pull-up to VDDP. Float or tie to VSSP when not used.
6 FLT1 O Fault 1 indicator. Open-drain output. When being used, requires external pull-up to VDDP. Float or tie to VSSP when not used.
7 ALM1 O Alarm 1 indicator. Open-drain output. When being used, requires external pull-up to VDDP. Float or tie to VSSP when not used.
8 VSSP GND Ground supply for the primary side. All VSSP must be connected to the primary side ground.
9 VSSS GND Ground supply for the secondary side. All VSSS pins must be connected to the secondary side ground.
10 RESP O Used in conjunction with an external resistor connected to VSSS to adjust comparator response time. When not being used, tie to VSSS.
11 ALM1_CMP I Analog comparator input. When ALM1_CMP voltage exceeds internal reference voltage, ALM1 is asserted low within tALM_LATENCY. Internal 2.8MΩ pull-down to VSSS. When not being used, tie to VSSS.
12 FLT1_CMP I Analog comparator input. When FLT1_CMP voltage exceeds internal reference voltage, VDRV is automatically asserted low regardless of EN state and FLT1 asserted low within tFLT_LATENCY. Internal 2.8MΩ pull-down to VSSS. When not being used, tie to VSSS.
13 VDDM P Generated mid-supply, nominal 5V.
14 VSSS GND Ground supply for secondary side. All VSSS pins must be connected to the secondary side ground.
15 VDDH P Generated high supply, nominal 17V.
16 VDRV O Active high driver output.
P = power, GND = ground, NC = no connect
TPSI3100-Q1 TPSI311x-Q1 and TPSI311xL-Q1DVX Package, 16-Pin SSOP(Top View) Figure 5-2 TPSI311x-Q1 and TPSI311xL-Q1DVX Package, 16-Pin SSOP(Top View)
PIN I/O TYPE(1) DESCRIPTION
NO. NAME
1 EN I Active high driver enable. Internal 500kΩ pull-down to VSSP.
2 CE I Active high input. When asserted low, device is disabled. Tie to VDDP when not used. Internal 500kΩ pull-down to VSSP.
3 VSSP GND Ground supply for primary side. All VSSP pins must be connected to the primary side ground.
4 VDDP P Power supply for the primary side.
5 PGOOD O Power good indicator. Open-drain output. When being used, requires external pull-up to VDDP. Float or tie to VSSP when not used.
6 FLT1 O Fault 1 indicator. Open-drain output. When being used, requires external pull-up to VDDP. Float or tie to VSSP when not used.
7 FLT2 O Fault 2 indicator. Open-drain output. When being used, requires external pull-up to VDDP. Float or tie to VSSP when not used.
8 VSSP GND Ground supply for the primary side. All VSSP pins must be connected to the primary side ground.
9 VSSS GND Ground supply for the secondary side. All VSSS pins must be connected to the secondary side ground.
10 RESP O Used in conjunction with an external resistor connected to VSSS to adjust comparator response time. When not being used, tie to VSSS.
11 FLT2_CMP I Analog comparator input. When FLT2_CMP voltage exceeds internal reference voltage, VDRV is automatically asserted low regardless of EN state and FLT2 asserted low within tFLT_LATENCY. Internal 2.8MΩ pull-down to VSSS. When not being used, tie to VSSS.
12 FLT1_CMP I Analog comparator input. When FLT1_CMP voltage exceeds internal reference voltage, VDRV is automatically asserted low regardless of EN state and FLT1 asserted low within tFLT_LATENCY. Internal 2.8MΩ pull-down to VSSS. When not being used, tie to VSSS.
13 VDDM P Generated mid-supply, nominal 5V.
14 VSSS GND Ground supply for secondary side. All VSSS pins must be connected to the secondary side ground.
15 VDDH P Generated high supply, nominal 17V.
16 VDRV O Active high driver output.
TPSI3100-Q1 TPSI312x-Q1
                    DVX Package, 16-Pin SSOP(Top View) Figure 5-3 TPSI312x-Q1 DVX Package, 16-Pin SSOP(Top View)
PIN I/O TYPE(1) DESCRIPTION
NO. NAME
1 EN I Active high driver enable. Internal 500kΩ pull-down to VSSP.
2 CE I Active high input. When asserted low, device is disabled. Tie to VDDP when not used. Internal 500kΩ pull-down to VSSP.
3 VSSP GND Ground supply for primary side. All VSSP pins must be connected to the primary side ground.
4 VDDP P Power supply for the primary side.
5 PGOOD O Power good indicator. Open-drain output. When being used, requires external pull-up to VDDP. Float or tie to VSSP when not used.
6 ALM1 O Alarm 1 indicator. Open-drain output. When being used, requires external pull-up to VDDP. Float or tie to VSSP when not used.
7 ALM2 O Alarm 2 indicator. Open-drain output. When being used, requires external pull-up to VDDP. Float or tie to VSSP when not used.
8 VSSP GND Ground supply for the primary side. All VSSP pins must be connected to the primary side ground.
9 VSSS GND Ground supply for the secondary side. All VSSS pins must be connected to the secondary side ground.
10 RESP O Used in conjunction with an external resistor connected to VSSS to adjust comparator response time. When not being used, tie to VSSS.
11 ALM2_CMP I Analog comparator input. When ALM2_CMP voltage exceeds internal reference voltage, ALM2 is asserted low within tALM_LATENCY. Internal 2.8MΩ pull-down to VSSS. When not being used, tie to VSSS.
12 ALM1_CMP I Analog comparator input. When ALM1_CMP voltage exceeds internal reference voltage, ALM1 is asserted low within tALM_LATENCY. Internal 2.8MΩ pull-down to VSSS. When not being used, tie to VSSS.
13 VDDM P Generated mid-supply, nominal 5V.
14 VSSS GND Ground supply for secondary side. All VSSS pins must be connected to the secondary side ground.
15 VDDH P Generated high supply, nominal 17V.
16 VDRV O Active high driver output.
TPSI3100-Q1 TPSI3133-Q1
                    DVX Package, 16-Pin SSOP(Top View) Figure 5-4 TPSI3133-Q1 DVX Package, 16-Pin SSOP(Top View)
PIN I/O TYPE(1) DESCRIPTION
NO. NAME
1 EN I Active high driver enable. Internal 500kΩ pull-down to VSSP.
2 CE I Active high input. When asserted low, device is disabled. Tie to VDDP when not used. Internal 500kΩ pull-down to VSSP.
3 VSSP GND Ground supply for primary side. All VSSP pins must be connected to the primary side ground.
4 VDDP P Power supply for the primary side.
5 PGOOD O Power good indicator. Open-drain output. When being used, requires external pull-up to VDDP. Float or tie to VSSP when not used.
6 FLT1 O Fault 1 indicator. Open-drain output. When being used, requires external pull-up to VDDP. Float or tie to VSSP when not used.
7 ALM1 O Alarm 1 indicator. Open-drain output. When being used, requires external pull-up to VDDP. Float or tie to VSSP when not used.
8 VSSP GND Ground supply for the primary side. All VSSP pins must be connected to the primary side ground.
9 VSSS GND Ground supply for the secondary side. All VSSS pins must be connected to the secondary side ground.
10 RESP O Used in conjunction with an external resistor connected to VSSS to adjust comparator response time. When not being used, tie to VSSS.
11 ALM1_CMP I Analog comparator input. When ALM1_CMP voltage exceeds internal reference voltage, ALM1 is asserted low within tALM_LATENCY. Internal 2.8MΩ pull-down to VSSS. When not being used, tie to VSSS.
12 FLT1_CMP I/O Analog comparator input/output. When EN state is low, FLT1_CMP is actively pulled low. If EN state is high and FLT1_CMP voltage exceeds internal reference voltage, VDRV is automatically asserted low and FLT1 asserted low within tFLT_LATENCY. Internal 2.8MΩ pull-down to VSSS. When not being used, tie to VSSS.
13 VDDM P Generated mid-supply, nominal 5V.
14 VSSS GND Ground supply for secondary side. All VSSS pins must be connected to the secondary side ground.
15 VDDH P Generated high supply, nominal 17V.
16 VDRV O Active high driver output.