SLVSG43A December   2023  – November 2024 TPSI3100-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Insulation Characteristic Curves
    12. 6.12 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Transmission of the Enable State
      2. 8.3.2 Power Transmission
      3. 8.3.3 Gate Driver
      4. 8.3.4 Chip Enable (CE)
      5. 8.3.5 Comparators
        1. 8.3.5.1 Fault Comparator
        2. 8.3.5.2 Alarm Comparator
        3. 8.3.5.3 Comparator De-glitch
      6. 8.3.6 VDDP, VDDH, and VDDM Undervoltage Lockout (UVLO)
      7. 8.3.7 Keep-Off Circuitry
      8. 8.3.8 Thermal Shutdown
    4. 8.4 Device Operation
    5. 8.5 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 CDIV1, CDIV2 Capacitance
        2. 9.2.2.2 Start-up Time and Recovery Time
        3. 9.2.2.3 RSHUNT, R1, and R2 Selection
        4. 9.2.2.4 Overcurrent Fault Error
        5. 9.2.2.5 Overcurrent Alarm Error
        6. 9.2.2.6 VDDP Capacitance, CVDDP
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DVX|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VDDP Primary side supply voltage(1) 4.5 5.5 V
EN Enable VDRV(1)
(1)		 0 5.5 V
CE Chip enable(1) 0 5.5 V
PGOOD Power good indicator(4)(1) 0 5.5 V
FLTn
 Fault indicator(s).(4)(1)
FLT1 (TPSI310x, TPSI311x, TPSI3133)
FLT2 (TPSI311x)
 0 5.5 V
ALMn
 Alarm indicator(s).(4)(1)
ALM1 (TPSI310x, TPSI311x, TPSI3133)
ALM2 (TPSI312x)
 0 5.5 V
CVDDP Decoupling capacitance on VDDP and VSSP(3) 1 20 µF
CDIV1(2) Decoupling capacitance across VDDH and VDDM(3) 0.003 15 µF
CDIV2(2) Decoupling capacitance across VDDM and VSSS(3) 0.1 40 µF
QTOTAL Total charge to be driven by VDRV. 2500 nC
RRESP Comparator response resistor from RESP to VSSS. 0 1000 kΩ
IAUX Auxiliary current sourced from VDDM. 0 5 mA
TA Ambient operating temperature –40 125 °C
TJ Operating junction temperature –40 150 °C
(1) All voltage values are with respect to VSSP.
(2) CDIV1 and CDIV2 should be of same type and tolerance. CDIV2 capacitance value should be at least three times the capacitance value of CDIV1 i.e. CDIV2 ≥ 3 × CDIV1.
(3) All capacitance values are absolute. Derating should be applied where necessary.
(4) Open-drain fail-safe output. When being used, an external pull-up resistor greater than 20kΩ to VDDP is recommended. When not being used, float pin or connect to VSSP.