SLVSG43A December   2023  – November 2024 TPSI3100-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Insulation Characteristic Curves
    12. 6.12 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Transmission of the Enable State
      2. 8.3.2 Power Transmission
      3. 8.3.3 Gate Driver
      4. 8.3.4 Chip Enable (CE)
      5. 8.3.5 Comparators
        1. 8.3.5.1 Fault Comparator
        2. 8.3.5.2 Alarm Comparator
        3. 8.3.5.3 Comparator De-glitch
      6. 8.3.6 VDDP, VDDH, and VDDM Undervoltage Lockout (UVLO)
      7. 8.3.7 Keep-Off Circuitry
      8. 8.3.8 Thermal Shutdown
    4. 8.4 Device Operation
    5. 8.5 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 CDIV1, CDIV2 Capacitance
        2. 9.2.2.2 Start-up Time and Recovery Time
        3. 9.2.2.3 RSHUNT, R1, and R2 Selection
        4. 9.2.2.4 Overcurrent Fault Error
        5. 9.2.2.5 Overcurrent Alarm Error
        6. 9.2.2.6 VDDP Capacitance, CVDDP
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DVX|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.10 Switching Characteristics

over operating free-air temperature range (unless otherwise noted). Typicals at TA = 25℃. CVDDP = 1µF, CDIV1 = 47nF, CDIV2 = 220nF,  CVDRV = 1nF, IAUX = 0mA. 50kΩ pull-ups from FLT1, ALM1, PGOOD to VDDP. RRESP = 100kΩ to VSSS.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER and DRIVER
tLO_CE Low time of CE.  VVDDH, VVDDM = steady state. 5 µs
tLO_EN Low time of EN.  VVDDH, VVDDM = steady state. 5 µs
tHI_EN High time of EN.  VVDDH, VVDDM = steady state. 5 µs
tPER_EN Period of EN.  VVDDH, VVDDM = steady state. 10 µs
tLH_VDDH Propagation delay time from VDDP rising to VDDH at 50% level. EN = 0V,
VVDDP =  0V → 5V at 1V/µs,
VVDDH = 7.5V.		 145 µs
tLH_VDRV Propagation delay time from EN rising to VDRV at 90% level VVDDP = 5V,
 VVDDH, VVDDM = steady state,
EN = 0V → 5V,
VVDRV = 13.5V.		 3 4.5 µs
tHL_VDRV Propagation delay time from EN falling to VDRV at 10% level VVDDP = 5V,
VVDDH, VVDDM = steady state,
EN = 5V → 0V,
VVDRV = 1.5V.		 2.5 3.0 µs
tHL_VDRV_PD Propagation delay time from VDDP falling to VDRV at 10% level. Timeout mechanism due to loss of power on primary supply. EN = 5V,
VVDDP =  5V → 0V at -1V/µs,
VVDRV = 1.5V.		 140 210 µs
tLH_VDRV_CE Propagation delay time from CE rising to VDRV at 10% level VVDDP = 5V,
VDDH and VDDM fully discharged.
EN = CE = 0V → 5V,
VVDRV = 1.5V.		 185 µs
tHL_VDRV_CE Propagation delay time from CE falling to VDRV at 10% level VVDDP = 5V,
VVDDH, VVDDM = steady state,
EN = 5V,
CE= 5V → 0V,
VVDRV = 1.5V.		 3 4 µs
tR_VDRV VDRV rise time from EN rising to VDRV from 15% to 85% level VVDDP = 5V,
VVDDH, VVDDM = steady state,
EN =  0V → 5V,
VVDRV = 2.25V to 12.75V.		 10 ns
tF_VDRV VDRV fall time from EN falling to VDRV from 85% to 15% level VVDDP = xV,
VVDDH, VVDDM = steady state,
EN = xV → 0V,
VVDRV = 12.75V to 2.25V.		 10 ns
tREC_VDRV(1) Time VDRV remains low upon detection of a fault condition. VVDDP = 5V,
VVDDH and VVDRV in steady state,
EN = 5V,
FLTn_CMP positive-pulse of 3V, 50µs pulse-width.
Measure from FLTn_CMP going low (1.5V) to VVDRV = 7.5V.		 165 270 µs
COMPARATORS
tPD_CMP_VDRV_DIS Propagation delay time, fault comparator output rising to VDRV asserted low. EN = CE = VDDP
RRESP ≤ 10kΩ
VUD = 100mV
VOD = 30mV
Measure VFLT_CMP crossing VREF to 50% VVDRV.		 320 385 460 ns
EN = CE = VDDP
RRESP = 100kΩ.
VUD = 100mV
VOD = 30mV
Measure VFLT_CMP crossing VREF to 50% VVDRV.		 630 715 830 ns
EN = CE = VDDP
RRESP = 300kΩ.
VUD = 100mV
VOD = 30mV
Measure VFLT_CMP crossing VREF to 50% VVDRV.		 890 1375 1970 ns
EN = CE = VDDP
RRESP = 500kΩ.
VUD = 100mV
VOD = 30mV
Measure VFLT_CMP crossing VREF to 50% VVDRV.		 1275 2020 2950 ns
tDEGLITCH_CMP_F Fault comparator falling output de-glitch. 4.2 5.7 8 µs
tFLT_LATENCY Delay from rising or falling event detected by fault comparator and indicated on FLT1 output. EN = CE = VDDP
RRESP = 500kΩ.
VUD = 100mV
VOD = 30mV
Measure VFLT1_CMP rising or falling and crossing VREF to 50% FLT1.		 30 µs
tALM_LATENCY Delay from rising or falling event detected by alarm comparator and indicated on ALM1 output. EN = CE = VDDP
RRESP = 500kΩ.
VUD = 100mV
VOD = 30mV
Measure VALM1_CMP rising or falling and crossing VREF to 50% ALM1.		 30 µs
(1) On latched based devices, recovery timer is still in effect even though VDRV is latched low. If the fault condition is removed and EN is asserted low and then high to clear the fault, VDRV will remain asserted low until the recovery timer has elapsed.