SLVSHN4 December   2023 TPSI3100

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Insulation Characteristic Curves
    12. 6.12 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Transmission of the Enable State
      2. 8.3.2 Power Transmission
      3. 8.3.3 Gate Driver
      4. 8.3.4 Chip Enable (CE)
      5. 8.3.5 Comparators
        1. 8.3.5.1 Fault Comparator
        2. 8.3.5.2 Alarm Comparator
        3. 8.3.5.3 Comparator De-glitch
      6. 8.3.6 VDDP, VDDH, and VDDM Under-voltage Lockout (UVLO)
      7. 8.3.7 Thermal Shutdown
    4. 8.4 Device Operation
    5. 8.5 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 CDIV1, CDIV2 Capacitance
        2. 9.2.2.2 Start-up Time and Recovery Time
        3. 9.2.2.3 RSHUNT, R1, and R2 Selection
        4. 9.2.2.4 Over-current Fault Error
        5. 9.2.2.5 Over-current Alarm Error
        6. 9.2.2.6 VDDP Capacitance, CVDDP
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
  • DVX|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.2.3 RSHUNT, R1, and R2 Selection

The TPSI3100 has an internal nominal voltage reference (VREF) of 0.3 V. This reference is shared by the fault and alarm comparator negative inputs. To minimize the RSHUNT resistance value and hence its associated power dissipation, a current sense amplifier is used that has a gain (GCSA) of 20 V/V.

The alarm event should be detected when the load current, ILOAD, reaches 5 A nominal. This corresponds to a voltage input to the current sense amplifier (VSENSE_ALM) of:

Equation 6. V S E N S E _ A L M = V R E F G C S A = 0.3 V 20 = 15   m V

From this, the nominal shunt resistance, RSHUNT may be calculated:

Equation 7. R S H U N T = V S E N S E _ A L M I L O A D = 15 m V 5 A = 3   m Ω

The corresponding power prior to an over-current condition due to the shunt resistor may be calculated:

Equation 8. P S H U N T = I O C P 2 × R S H U N T = ( 10   A ) 2 × 3   m Ω = 300   m W  

The power dissipated in the shunt resistor is below the design requirement of 0.5 W.

The fault event should be detected when the load current, ILOAD, reaches 10 A nominal. This corresponds to a voltage input to the current sense amplifier (VSENSE_FLT) of:

Equation 9. V S E N S E _ F L T = R S H U N T × I L O A D = 3   m Ω × 10 A = 30   m V

The resulting output of the current sense amplifier (VCSA_FLT) is:

Equation 10. V C S A _ F L T = V S E N S E _ F L T × G C S A = 30   m V × 20 = 0.6   V

Since the fault comparator threshold of the TPSI3100 is 0.3 V, a resistor divider is required to scale the current sense amplifier output voltage (VCSA_FLT) to the comparator input threshold (VREF). The divider ratio (DIV) required can be calculated from:

Equation 11. D I V = V R E F R S H U N T × I L O A D × G C S A = V R E F V C S A _ F L T = 0.5
Equation 12. D I V = R 2 R 1 + R 2