SNVSCI1A October   2023  – December 2023 TPSM365R1 , TPSM365R15

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 System Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Enable, Shutdown, and Start-Up
      2. 7.3.2  External CLK SYNC (With MODE/SYNC)
        1. 7.3.2.1 Pulse Dependent MODE/SYNC Pin Control
      3. 7.3.3  Adjustable Switching Frequency (with RT)
      4. 7.3.4  Power-Good Output Operation
      5. 7.3.5  Internal LDO, VCC UVLO, and VOUT/FB Input
      6. 7.3.6  Bootstrap Voltage and VBOOT-UVLO (BOOT Terminal)
      7. 7.3.7  Output Voltage Selection
      8. 7.3.8  Spread Spectrum
      9. 7.3.9  Soft Start and Recovery from Dropout
        1. 7.3.9.1 Soft Start
        2. 7.3.9.2 Recovery from Dropout
      10. 7.3.10 Current Limit and Short Circuit
      11. 7.3.11 Thermal Shutdown
      12. 7.3.12 Input Supply Current
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Active Mode
        1. 7.4.3.1 CCM Mode
        2. 7.4.3.2 AUTO Mode - Light Load Operation
          1. 7.4.3.2.1 Diode Emulation
          2. 7.4.3.2.2 Frequency Reduction
        3. 7.4.3.3 FPWM Mode - Light Load Operation
        4. 7.4.3.4 Minimum On-time Operation
        5. 7.4.3.5 Dropout
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  Choosing the Switching Frequency
        3. 8.2.2.3  Setting the Output Voltage
        4. 8.2.2.4  Input Capacitor Selection
        5. 8.2.2.5  Output Capacitor Selection
        6. 8.2.2.6  VCC
        7. 8.2.2.7  CFF Selection
        8. 8.2.2.8  External UVLO
        9. 8.2.2.9  Power-Good Signal
        10. 8.2.2.10 Maximum Ambient Temperature
        11. 8.2.2.11 Other Connections
      3. 8.2.3 Application Curves
    3. 8.3 Best Design Practices
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Device Nomenclature
      2. 9.1.2 Development Support
        1. 9.1.2.1 Custom Design With WEBENCH® Tools
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.5.1 Layout Guidelines

The PCB layout of any DC/DC module is critical to the optimal performance of the design. Poor PCB layout can disrupt the operation of an otherwise good schematic design. Even if the module regulates correctly, bad PCB layout can mean the difference between a robust design and one that cannot be mass produced. Furthermore, to a great extent, the EMI performance of the regulator is dependent on the PCB layout. In a buck converter module, the most critical PCB feature is the loop formed by the input capacitor or capacitors and power ground, as shown in Figure 8-15. This loop carries large transient currents that can cause large transient voltages when reacting with the trace inductance. These unwanted transient voltages disrupt the proper operation of the power module. Because of this, the traces in this loop must be wide and short, and the loop area as small as possible to reduce the parasitic inductance. Layout Example shows a recommended layout for the critical components of the TPSM365R15.

  1. Place the input capacitors as close as possible to the VIN and GND terminals. VIN and GND pins are adjacent, simplifying the input capacitor placement.
  2. Place bypass capacitor for VCC close to the VCC pin. This capacitor must be placed close to the device and routed with short, wide traces to the VCC and GND pins.
  3. Place the feedback divider as close as possible to the FB pin of the device. Place RFBB, RFBT, and CFF, if used, physically close to the device. The connections to FB and GND must be short and close to those pins on the device. The connection to VOUT can be somewhat longer. However, the latter trace must not be routed near any noise source (such as the SW node) that can capacitively couple into the feedback path of the regulator.
  4. Use at least one ground plane in one of the middle layers. This plane acts as a noise shield and as a heat dissipation path.
  5. Provide wide paths for VIN, VOUT, and GND. Making these paths as wide and direct as possible reduces any voltage drops on the input or output paths of the power module and maximizes efficiency.
  6. Provide enough PCB area for proper heat-sinking. Sufficient amount of copper area must be used to make sure of a low RθJA, commensurate with the maximum load current and ambient temperature. The top and bottom PCB layers must be made with two ounce copper and no less than one ounce. If the PCB design uses multiple copper layers (recommended), these thermal vias can also be connected to the inner layer heat-spreading ground planes.
  7. Use multiple vias to connect the power planes to internal layers.

See the following PCB layout resources for additional important guidelines:

GUID-20221129-SS0I-DTVV-PJ8T-5S2LJHFJS1M0-low.svg Figure 8-15 Current Loops with Fast Edges